forked from Minki/linux
e325d76f8b
The function pnv_restore_hyp_resource() loads the TOC into r2 from
the invalid PACA pointer before fixing r13 value. This do not affect
POWER ISA 3.0 but it does have an impact on POWER ISA 2.07 or less
leading CPU to get stuck forever.
login: [ 471.830433] Processor 120 is stuck.
This can be easily reproducible using following steps:
- Turn off SMT
$ ppc64_cpu --smt=off
- offline/online any online cpu (Thread 0 of any core which is online)
$ echo 0 > /sys/devices/system/cpu/cpu<num>/online
$ echo 1 > /sys/devices/system/cpu/cpu<num>/online
For POWER ISA 2.07 or less, the last bit of HSPRG0 is set indicating
that thread is waking up from winkle. Hence, the last bit of HSPRG0(r13)
needs to be clear before accessing it as PACA to avoid loading invalid
values from invalid PACA pointer.
Fix this by loading TOC after r13 register is corrected.
Fixes: bcef83a00d ("powerpc/powernv: Add platform support for stop instruction")
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Acked-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
668 lines
16 KiB
ArmAsm
668 lines
16 KiB
ArmAsm
/*
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* This file contains idle entry/exit functions for POWER7,
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* POWER8 and POWER9 CPUs.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/threads.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/ppc-opcode.h>
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#include <asm/hw_irq.h>
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#include <asm/kvm_book3s_asm.h>
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#include <asm/opal.h>
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#include <asm/cpuidle.h>
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#include <asm/book3s/64/mmu-hash.h>
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#include <asm/mmu.h>
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#undef DEBUG
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/*
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* Use unused space in the interrupt stack to save and restore
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* registers for winkle support.
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*/
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#define _SDR1 GPR3
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#define _RPR GPR4
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#define _SPURR GPR5
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#define _PURR GPR6
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#define _TSCR GPR7
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#define _DSCR GPR8
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#define _AMOR GPR9
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#define _WORT GPR10
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#define _WORC GPR11
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#define _PTCR GPR12
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#define PSSCR_HV_TEMPLATE PSSCR_ESL | PSSCR_EC | \
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PSSCR_PSLL_MASK | PSSCR_TR_MASK | \
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PSSCR_MTL_MASK
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/* Idle state entry routines */
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#define IDLE_STATE_ENTER_SEQ(IDLE_INST) \
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/* Magic NAP/SLEEP/WINKLE mode enter sequence */ \
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std r0,0(r1); \
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ptesync; \
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ld r0,0(r1); \
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1: cmp cr0,r0,r0; \
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bne 1b; \
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IDLE_INST; \
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b .
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.text
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/*
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* Used by threads before entering deep idle states. Saves SPRs
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* in interrupt stack frame
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*/
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save_sprs_to_stack:
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/*
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* Note all register i.e per-core, per-subcore or per-thread is saved
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* here since any thread in the core might wake up first
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*/
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BEGIN_FTR_SECTION
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mfspr r3,SPRN_PTCR
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std r3,_PTCR(r1)
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/*
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* Note - SDR1 is dropped in Power ISA v3. Hence not restoring
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* SDR1 here
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*/
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FTR_SECTION_ELSE
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mfspr r3,SPRN_SDR1
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std r3,_SDR1(r1)
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
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mfspr r3,SPRN_RPR
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std r3,_RPR(r1)
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mfspr r3,SPRN_SPURR
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std r3,_SPURR(r1)
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mfspr r3,SPRN_PURR
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std r3,_PURR(r1)
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mfspr r3,SPRN_TSCR
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std r3,_TSCR(r1)
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mfspr r3,SPRN_DSCR
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std r3,_DSCR(r1)
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mfspr r3,SPRN_AMOR
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std r3,_AMOR(r1)
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mfspr r3,SPRN_WORT
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std r3,_WORT(r1)
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mfspr r3,SPRN_WORC
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std r3,_WORC(r1)
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blr
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/*
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* Used by threads when the lock bit of core_idle_state is set.
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* Threads will spin in HMT_LOW until the lock bit is cleared.
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* r14 - pointer to core_idle_state
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* r15 - used to load contents of core_idle_state
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*/
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core_idle_lock_held:
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HMT_LOW
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3: lwz r15,0(r14)
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andi. r15,r15,PNV_CORE_IDLE_LOCK_BIT
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bne 3b
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HMT_MEDIUM
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lwarx r15,0,r14
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blr
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/*
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* Pass requested state in r3:
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* r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
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* - Requested STOP state in POWER9
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*
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* To check IRQ_HAPPENED in r4
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* 0 - don't check
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* 1 - check
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*
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* Address to 'rfid' to in r5
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*/
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_GLOBAL(pnv_powersave_common)
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/* Use r3 to pass state nap/sleep/winkle */
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/* NAP is a state loss, we create a regs frame on the
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* stack, fill it up with the state we care about and
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* stick a pointer to it in PACAR1. We really only
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* need to save PC, some CR bits and the NV GPRs,
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* but for now an interrupt frame will do.
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*/
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mflr r0
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std r0,16(r1)
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stdu r1,-INT_FRAME_SIZE(r1)
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std r0,_LINK(r1)
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std r0,_NIP(r1)
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/* Hard disable interrupts */
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mfmsr r9
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rldicl r9,r9,48,1
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rotldi r9,r9,16
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mtmsrd r9,1 /* hard-disable interrupts */
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/* Check if something happened while soft-disabled */
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lbz r0,PACAIRQHAPPENED(r13)
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andi. r0,r0,~PACA_IRQ_HARD_DIS@l
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beq 1f
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cmpwi cr0,r4,0
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beq 1f
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addi r1,r1,INT_FRAME_SIZE
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ld r0,16(r1)
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li r3,0 /* Return 0 (no nap) */
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mtlr r0
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blr
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1: /* We mark irqs hard disabled as this is the state we'll
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* be in when returning and we need to tell arch_local_irq_restore()
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* about it
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*/
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li r0,PACA_IRQ_HARD_DIS
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stb r0,PACAIRQHAPPENED(r13)
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/* We haven't lost state ... yet */
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li r0,0
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stb r0,PACA_NAPSTATELOST(r13)
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/* Continue saving state */
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SAVE_GPR(2, r1)
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SAVE_NVGPRS(r1)
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mfcr r4
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std r4,_CCR(r1)
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std r9,_MSR(r1)
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std r1,PACAR1(r13)
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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/* Tell KVM we're entering idle */
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li r4,KVM_HWTHREAD_IN_IDLE
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stb r4,HSTATE_HWTHREAD_STATE(r13)
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#endif
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/*
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* Go to real mode to do the nap, as required by the architecture.
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* Also, we need to be in real mode before setting hwthread_state,
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* because as soon as we do that, another thread can switch
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* the MMU context to the guest.
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*/
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LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
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li r6, MSR_RI
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andc r6, r9, r6
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mtmsrd r6, 1 /* clear RI before setting SRR0/1 */
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mtspr SPRN_SRR0, r5
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mtspr SPRN_SRR1, r7
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rfid
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.globl pnv_enter_arch207_idle_mode
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pnv_enter_arch207_idle_mode:
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stb r3,PACA_THREAD_IDLE_STATE(r13)
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cmpwi cr3,r3,PNV_THREAD_SLEEP
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bge cr3,2f
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IDLE_STATE_ENTER_SEQ(PPC_NAP)
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/* No return */
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2:
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/* Sleep or winkle */
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lbz r7,PACA_THREAD_MASK(r13)
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ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
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lwarx_loop1:
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lwarx r15,0,r14
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andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
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bnel core_idle_lock_held
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andc r15,r15,r7 /* Clear thread bit */
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andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
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/*
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* If cr0 = 0, then current thread is the last thread of the core entering
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* sleep. Last thread needs to execute the hardware bug workaround code if
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* required by the platform.
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* Make the workaround call unconditionally here. The below branch call is
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* patched out when the idle states are discovered if the platform does not
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* require it.
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*/
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.global pnv_fastsleep_workaround_at_entry
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pnv_fastsleep_workaround_at_entry:
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beq fastsleep_workaround_at_entry
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stwcx. r15,0,r14
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bne- lwarx_loop1
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isync
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common_enter: /* common code for all the threads entering sleep or winkle */
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bgt cr3,enter_winkle
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IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
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fastsleep_workaround_at_entry:
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ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
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stwcx. r15,0,r14
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bne- lwarx_loop1
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isync
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/* Fast sleep workaround */
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li r3,1
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li r4,1
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bl opal_rm_config_cpu_idle_state
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/* Clear Lock bit */
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li r0,0
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lwsync
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stw r0,0(r14)
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b common_enter
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enter_winkle:
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bl save_sprs_to_stack
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IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
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/*
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* r3 - requested stop state
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*/
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power_enter_stop:
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/*
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* Check if the requested state is a deep idle state.
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*/
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LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
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ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
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cmpd r3,r4
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bge 2f
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IDLE_STATE_ENTER_SEQ(PPC_STOP)
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2:
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/*
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* Entering deep idle state.
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* Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
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* stack and enter stop
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*/
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lbz r7,PACA_THREAD_MASK(r13)
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ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
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lwarx_loop_stop:
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lwarx r15,0,r14
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andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
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bnel core_idle_lock_held
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andc r15,r15,r7 /* Clear thread bit */
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stwcx. r15,0,r14
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bne- lwarx_loop_stop
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isync
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bl save_sprs_to_stack
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IDLE_STATE_ENTER_SEQ(PPC_STOP)
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_GLOBAL(power7_idle)
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/* Now check if user or arch enabled NAP mode */
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LOAD_REG_ADDRBASE(r3,powersave_nap)
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lwz r4,ADDROFF(powersave_nap)(r3)
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cmpwi 0,r4,0
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beqlr
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li r3, 1
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/* fall through */
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_GLOBAL(power7_nap)
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mr r4,r3
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li r3,PNV_THREAD_NAP
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LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
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b pnv_powersave_common
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/* No return */
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_GLOBAL(power7_sleep)
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li r3,PNV_THREAD_SLEEP
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li r4,1
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LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
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b pnv_powersave_common
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/* No return */
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_GLOBAL(power7_winkle)
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li r3,PNV_THREAD_WINKLE
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li r4,1
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LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
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b pnv_powersave_common
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/* No return */
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#define CHECK_HMI_INTERRUPT \
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mfspr r0,SPRN_SRR1; \
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BEGIN_FTR_SECTION_NESTED(66); \
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rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
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FTR_SECTION_ELSE_NESTED(66); \
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rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
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ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
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cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
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bne 20f; \
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/* Invoke opal call to handle hmi */ \
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ld r2,PACATOC(r13); \
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ld r1,PACAR1(r13); \
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std r3,ORIG_GPR3(r1); /* Save original r3 */ \
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li r3,0; /* NULL argument */ \
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bl hmi_exception_realmode; \
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nop; \
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ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
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20: nop;
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/*
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* r3 - requested stop state
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*/
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_GLOBAL(power9_idle_stop)
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LOAD_REG_IMMEDIATE(r4, PSSCR_HV_TEMPLATE)
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or r4,r4,r3
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mtspr SPRN_PSSCR, r4
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li r4, 1
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LOAD_REG_ADDR(r5,power_enter_stop)
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b pnv_powersave_common
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/* No return */
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/*
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* Called from reset vector. Check whether we have woken up with
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* hypervisor state loss. If yes, restore hypervisor state and return
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* back to reset vector.
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*
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* r13 - Contents of HSPRG0
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* cr3 - set to gt if waking up with partial/complete hypervisor state loss
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*/
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_GLOBAL(pnv_restore_hyp_resource)
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BEGIN_FTR_SECTION
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ld r2,PACATOC(r13);
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/*
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* POWER ISA 3. Use PSSCR to determine if we
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* are waking up from deep idle state
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*/
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LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
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ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
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mfspr r5,SPRN_PSSCR
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/*
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* 0-3 bits correspond to Power-Saving Level Status
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* which indicates the idle state we are waking up from
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*/
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rldicl r5,r5,4,60
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cmpd cr4,r5,r4
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bge cr4,pnv_wakeup_tb_loss
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/*
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* Waking up without hypervisor state loss. Return to
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* reset vector
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*/
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blr
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
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/*
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* POWER ISA 2.07 or less.
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* Check if last bit of HSPGR0 is set. This indicates whether we are
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* waking up from winkle.
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*/
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clrldi r5,r13,63
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clrrdi r13,r13,1
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/* Now that we are sure r13 is corrected, load TOC */
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ld r2,PACATOC(r13);
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cmpwi cr4,r5,1
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mtspr SPRN_HSPRG0,r13
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lbz r0,PACA_THREAD_IDLE_STATE(r13)
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cmpwi cr2,r0,PNV_THREAD_NAP
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bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
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/*
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* We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
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* up from nap. At this stage CR3 shouldn't contains 'gt' since that
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* indicates we are waking with hypervisor state loss from nap.
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*/
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bgt cr3,.
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blr /* Return back to System Reset vector from where
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pnv_restore_hyp_resource was invoked */
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/*
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* Called if waking up from idle state which can cause either partial or
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* complete hyp state loss.
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* In POWER8, called if waking up from fastsleep or winkle
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* In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
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*
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* r13 - PACA
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* cr3 - gt if waking up with partial/complete hypervisor state loss
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* cr4 - eq if waking up from complete hypervisor state loss.
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*/
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_GLOBAL(pnv_wakeup_tb_loss)
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ld r1,PACAR1(r13)
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/*
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* Before entering any idle state, the NVGPRs are saved in the stack
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* and they are restored before switching to the process context. Hence
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* until they are restored, they are free to be used.
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*
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* Save SRR1 and LR in NVGPRs as they might be clobbered in
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* opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
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* to determine the wakeup reason if we branch to kvm_start_guest. LR
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* is required to return back to reset vector after hypervisor state
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* restore is complete.
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*/
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mflr r17
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mfspr r16,SPRN_SRR1
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BEGIN_FTR_SECTION
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CHECK_HMI_INTERRUPT
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END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
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lbz r7,PACA_THREAD_MASK(r13)
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ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
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lwarx_loop2:
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lwarx r15,0,r14
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andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
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/*
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* Lock bit is set in one of the 2 cases-
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* a. In the sleep/winkle enter path, the last thread is executing
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* fastsleep workaround code.
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* b. In the wake up path, another thread is executing fastsleep
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* workaround undo code or resyncing timebase or restoring context
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* In either case loop until the lock bit is cleared.
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*/
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bnel core_idle_lock_held
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cmpwi cr2,r15,0
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/*
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* At this stage
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* cr2 - eq if first thread to wakeup in core
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* cr3- gt if waking up with partial/complete hypervisor state loss
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* cr4 - eq if waking up from complete hypervisor state loss.
|
|
*/
|
|
|
|
ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
|
|
stwcx. r15,0,r14
|
|
bne- lwarx_loop2
|
|
isync
|
|
|
|
BEGIN_FTR_SECTION
|
|
lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
|
|
and r4,r4,r15
|
|
cmpwi r4,0 /* Check if first in subcore */
|
|
|
|
or r15,r15,r7 /* Set thread bit */
|
|
beq first_thread_in_subcore
|
|
END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
|
|
|
|
or r15,r15,r7 /* Set thread bit */
|
|
beq cr2,first_thread_in_core
|
|
|
|
/* Not first thread in core or subcore to wake up */
|
|
b clear_lock
|
|
|
|
first_thread_in_subcore:
|
|
/*
|
|
* If waking up from sleep, subcore state is not lost. Hence
|
|
* skip subcore state restore
|
|
*/
|
|
bne cr4,subcore_state_restored
|
|
|
|
/* Restore per-subcore state */
|
|
ld r4,_SDR1(r1)
|
|
mtspr SPRN_SDR1,r4
|
|
|
|
ld r4,_RPR(r1)
|
|
mtspr SPRN_RPR,r4
|
|
ld r4,_AMOR(r1)
|
|
mtspr SPRN_AMOR,r4
|
|
|
|
subcore_state_restored:
|
|
/*
|
|
* Check if the thread is also the first thread in the core. If not,
|
|
* skip to clear_lock.
|
|
*/
|
|
bne cr2,clear_lock
|
|
|
|
first_thread_in_core:
|
|
|
|
/*
|
|
* First thread in the core waking up from any state which can cause
|
|
* partial or complete hypervisor state loss. It needs to
|
|
* call the fastsleep workaround code if the platform requires it.
|
|
* Call it unconditionally here. The below branch instruction will
|
|
* be patched out if the platform does not have fastsleep or does not
|
|
* require the workaround. Patching will be performed during the
|
|
* discovery of idle-states.
|
|
*/
|
|
.global pnv_fastsleep_workaround_at_exit
|
|
pnv_fastsleep_workaround_at_exit:
|
|
b fastsleep_workaround_at_exit
|
|
|
|
timebase_resync:
|
|
/*
|
|
* Use cr3 which indicates that we are waking up with atleast partial
|
|
* hypervisor state loss to determine if TIMEBASE RESYNC is needed.
|
|
*/
|
|
ble cr3,clear_lock
|
|
/* Time base re-sync */
|
|
bl opal_rm_resync_timebase;
|
|
/*
|
|
* If waking up from sleep, per core state is not lost, skip to
|
|
* clear_lock.
|
|
*/
|
|
bne cr4,clear_lock
|
|
|
|
/*
|
|
* First thread in the core to wake up and its waking up with
|
|
* complete hypervisor state loss. Restore per core hypervisor
|
|
* state.
|
|
*/
|
|
BEGIN_FTR_SECTION
|
|
ld r4,_PTCR(r1)
|
|
mtspr SPRN_PTCR,r4
|
|
ld r4,_RPR(r1)
|
|
mtspr SPRN_RPR,r4
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
|
|
|
|
ld r4,_TSCR(r1)
|
|
mtspr SPRN_TSCR,r4
|
|
ld r4,_WORC(r1)
|
|
mtspr SPRN_WORC,r4
|
|
|
|
clear_lock:
|
|
andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
|
|
lwsync
|
|
stw r15,0(r14)
|
|
|
|
common_exit:
|
|
/*
|
|
* Common to all threads.
|
|
*
|
|
* If waking up from sleep, hypervisor state is not lost. Hence
|
|
* skip hypervisor state restore.
|
|
*/
|
|
bne cr4,hypervisor_state_restored
|
|
|
|
/* Waking up from winkle */
|
|
|
|
BEGIN_MMU_FTR_SECTION
|
|
b no_segments
|
|
END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
|
|
/* Restore SLB from PACA */
|
|
ld r8,PACA_SLBSHADOWPTR(r13)
|
|
|
|
.rept SLB_NUM_BOLTED
|
|
li r3, SLBSHADOW_SAVEAREA
|
|
LDX_BE r5, r8, r3
|
|
addi r3, r3, 8
|
|
LDX_BE r6, r8, r3
|
|
andis. r7,r5,SLB_ESID_V@h
|
|
beq 1f
|
|
slbmte r6,r5
|
|
1: addi r8,r8,16
|
|
.endr
|
|
no_segments:
|
|
|
|
/* Restore per thread state */
|
|
|
|
ld r4,_SPURR(r1)
|
|
mtspr SPRN_SPURR,r4
|
|
ld r4,_PURR(r1)
|
|
mtspr SPRN_PURR,r4
|
|
ld r4,_DSCR(r1)
|
|
mtspr SPRN_DSCR,r4
|
|
ld r4,_WORT(r1)
|
|
mtspr SPRN_WORT,r4
|
|
|
|
/* Call cur_cpu_spec->cpu_restore() */
|
|
LOAD_REG_ADDR(r4, cur_cpu_spec)
|
|
ld r4,0(r4)
|
|
ld r12,CPU_SPEC_RESTORE(r4)
|
|
#ifdef PPC64_ELF_ABI_v1
|
|
ld r12,0(r12)
|
|
#endif
|
|
mtctr r12
|
|
bctrl
|
|
|
|
hypervisor_state_restored:
|
|
|
|
mtspr SPRN_SRR1,r16
|
|
mtlr r17
|
|
blr /* Return back to System Reset vector from where
|
|
pnv_restore_hyp_resource was invoked */
|
|
|
|
fastsleep_workaround_at_exit:
|
|
li r3,1
|
|
li r4,0
|
|
bl opal_rm_config_cpu_idle_state
|
|
b timebase_resync
|
|
|
|
/*
|
|
* R3 here contains the value that will be returned to the caller
|
|
* of power7_nap.
|
|
*/
|
|
_GLOBAL(pnv_wakeup_loss)
|
|
ld r1,PACAR1(r13)
|
|
BEGIN_FTR_SECTION
|
|
CHECK_HMI_INTERRUPT
|
|
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
|
|
REST_NVGPRS(r1)
|
|
REST_GPR(2, r1)
|
|
ld r6,_CCR(r1)
|
|
ld r4,_MSR(r1)
|
|
ld r5,_NIP(r1)
|
|
addi r1,r1,INT_FRAME_SIZE
|
|
mtcr r6
|
|
mtspr SPRN_SRR1,r4
|
|
mtspr SPRN_SRR0,r5
|
|
rfid
|
|
|
|
/*
|
|
* R3 here contains the value that will be returned to the caller
|
|
* of power7_nap.
|
|
*/
|
|
_GLOBAL(pnv_wakeup_noloss)
|
|
lbz r0,PACA_NAPSTATELOST(r13)
|
|
cmpwi r0,0
|
|
bne pnv_wakeup_loss
|
|
BEGIN_FTR_SECTION
|
|
CHECK_HMI_INTERRUPT
|
|
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
|
|
ld r1,PACAR1(r13)
|
|
ld r6,_CCR(r1)
|
|
ld r4,_MSR(r1)
|
|
ld r5,_NIP(r1)
|
|
addi r1,r1,INT_FRAME_SIZE
|
|
mtcr r6
|
|
mtspr SPRN_SRR1,r4
|
|
mtspr SPRN_SRR0,r5
|
|
rfid
|