e322423471
so we: 1. could set some cap to ap 2. restore some cap after memset in identify_cpu for boot cpu esp for CONSTANT_TSC this matters, as: before this patch: flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow rep_good nopl pni monitor cx16 lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs after this patch: flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc rep_good nopl pni monitor cx16 lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs so constant_tsc is back... Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
102 lines
2.2 KiB
C
102 lines
2.2 KiB
C
#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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#include <asm/topology.h>
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#include <asm/numa_64.h>
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#include "cpu.h"
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static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
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{
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if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
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(c->x86 == 0x6 && c->x86_model >= 0x0e))
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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set_cpu_cap(c, X86_FEATURE_SYSENTER32);
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}
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/*
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* find out the number of processor cores on the die
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*/
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static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
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{
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unsigned int eax, t;
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if (c->cpuid_level < 4)
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return 1;
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cpuid_count(4, 0, &eax, &t, &t, &t);
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if (eax & 0x1f)
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return ((eax >> 26) + 1);
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else
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return 1;
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}
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static void __cpuinit srat_detect_node(void)
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{
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#ifdef CONFIG_NUMA
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unsigned node;
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int cpu = smp_processor_id();
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int apicid = hard_smp_processor_id();
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/* Don't do the funky fallback heuristics the AMD version employs
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for now. */
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node = apicid_to_node[apicid];
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if (node == NUMA_NO_NODE || !node_online(node))
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node = first_node(node_online_map);
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numa_set_node(cpu, node);
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printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
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#endif
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}
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static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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{
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early_init_intel(c);
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init_intel_cacheinfo(c);
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if (c->cpuid_level > 9) {
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unsigned eax = cpuid_eax(10);
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/* Check for version and the number of counters */
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if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
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set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
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}
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if (cpu_has_ds) {
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unsigned int l1, l2;
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rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
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if (!(l1 & (1<<11)))
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set_cpu_cap(c, X86_FEATURE_BTS);
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if (!(l1 & (1<<12)))
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set_cpu_cap(c, X86_FEATURE_PEBS);
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}
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if (cpu_has_bts)
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ds_init_intel(c);
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if (c->x86 == 15)
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c->x86_cache_alignment = c->x86_clflush_size * 2;
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if (c->x86 == 6)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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detect_extended_topology(c);
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if (!cpu_has(c, X86_FEATURE_XTOPOLOGY))
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c->x86_max_cores = intel_num_cpu_cores(c);
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srat_detect_node();
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}
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static struct cpu_dev intel_cpu_dev __cpuinitdata = {
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.c_vendor = "Intel",
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.c_ident = { "GenuineIntel" },
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.c_early_init = early_init_intel,
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.c_init = init_intel,
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.c_x86_vendor = X86_VENDOR_INTEL,
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};
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cpu_dev_register(intel_cpu_dev);
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