Alexandru Ardelean e31b617d0a staging: iio: adc: ad7192: fix external frequency setting ... The external clock frequency was set only when selecting the internal clock, which is fixed at 4.9152 Mhz. This is incorrect, since it should be set when any of the external clock or crystal settings is selected. Added range validation for the external (crystal/clock) frequency setting. Valid values are between 2.4576 and 5.12 Mhz. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>		2018-01-28 08:16:24 +00:00
..
accel
adc	staging: iio: adc: ad7192: fix external frequency setting	2018-01-28 08:16:24 +00:00
addac
cdc	Staging: iio: cdc: ad7152: Prefer using BIT macro	2018-01-08 16:03:43 +01:00
Documentation
frequency
gyro
impedance-analyzer
light	staging: iio: light: Add breaks to lengthy lines	2018-01-08 16:03:44 +01:00
meter	Staging/IIO patches for 4.15-rc1	2017-11-13 20:53:28 -08:00
resolver
trigger	staging: iio: trigger: blackfin timer: replace device_attr with device_attr_rw	2018-01-08 16:03:43 +01:00
Kconfig
Makefile	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
TODO