forked from Minki/linux
e30ba89fdf
Name iomuxc sub-nodes following pin function and hardware manual. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
830 lines
20 KiB
Plaintext
830 lines
20 KiB
Plaintext
/*
|
|
* Copyright 2011 Freescale Semiconductor, Inc.
|
|
* Copyright 2011 Linaro Ltd.
|
|
*
|
|
* The code contained herein is licensed under the GNU General Public
|
|
* License. You may obtain a copy of the GNU General Public License
|
|
* Version 2 or later at the following locations:
|
|
*
|
|
* http://www.opensource.org/licenses/gpl-license.html
|
|
* http://www.gnu.org/copyleft/gpl.html
|
|
*/
|
|
|
|
/include/ "skeleton.dtsi"
|
|
|
|
/ {
|
|
aliases {
|
|
serial0 = &uart1;
|
|
serial1 = &uart2;
|
|
serial2 = &uart3;
|
|
serial3 = &uart4;
|
|
serial4 = &uart5;
|
|
gpio0 = &gpio1;
|
|
gpio1 = &gpio2;
|
|
gpio2 = &gpio3;
|
|
gpio3 = &gpio4;
|
|
gpio4 = &gpio5;
|
|
gpio5 = &gpio6;
|
|
gpio6 = &gpio7;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
compatible = "arm,cortex-a9";
|
|
reg = <0>;
|
|
next-level-cache = <&L2>;
|
|
};
|
|
|
|
cpu@1 {
|
|
compatible = "arm,cortex-a9";
|
|
reg = <1>;
|
|
next-level-cache = <&L2>;
|
|
};
|
|
|
|
cpu@2 {
|
|
compatible = "arm,cortex-a9";
|
|
reg = <2>;
|
|
next-level-cache = <&L2>;
|
|
};
|
|
|
|
cpu@3 {
|
|
compatible = "arm,cortex-a9";
|
|
reg = <3>;
|
|
next-level-cache = <&L2>;
|
|
};
|
|
};
|
|
|
|
intc: interrupt-controller@00a01000 {
|
|
compatible = "arm,cortex-a9-gic";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupt-controller;
|
|
reg = <0x00a01000 0x1000>,
|
|
<0x00a00100 0x100>;
|
|
};
|
|
|
|
clocks {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ckil {
|
|
compatible = "fsl,imx-ckil", "fixed-clock";
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
ckih1 {
|
|
compatible = "fsl,imx-ckih1", "fixed-clock";
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
osc {
|
|
compatible = "fsl,imx-osc", "fixed-clock";
|
|
clock-frequency = <24000000>;
|
|
};
|
|
};
|
|
|
|
soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "simple-bus";
|
|
interrupt-parent = <&intc>;
|
|
ranges;
|
|
|
|
dma-apbh@00110000 {
|
|
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
|
|
reg = <0x00110000 0x2000>;
|
|
};
|
|
|
|
gpmi-nand@00112000 {
|
|
compatible = "fsl,imx6q-gpmi-nand";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
|
|
reg-names = "gpmi-nand", "bch";
|
|
interrupts = <0 13 0x04>, <0 15 0x04>;
|
|
interrupt-names = "gpmi-dma", "bch";
|
|
fsl,gpmi-dma-channel = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@00a00600 {
|
|
compatible = "arm,cortex-a9-twd-timer";
|
|
reg = <0x00a00600 0x20>;
|
|
interrupts = <1 13 0xf01>;
|
|
};
|
|
|
|
L2: l2-cache@00a02000 {
|
|
compatible = "arm,pl310-cache";
|
|
reg = <0x00a02000 0x1000>;
|
|
interrupts = <0 92 0x04>;
|
|
cache-unified;
|
|
cache-level = <2>;
|
|
};
|
|
|
|
aips-bus@02000000 { /* AIPS1 */
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x02000000 0x100000>;
|
|
ranges;
|
|
|
|
spba-bus@02000000 {
|
|
compatible = "fsl,spba-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x02000000 0x40000>;
|
|
ranges;
|
|
|
|
spdif@02004000 {
|
|
reg = <0x02004000 0x4000>;
|
|
interrupts = <0 52 0x04>;
|
|
};
|
|
|
|
ecspi@02008000 { /* eCSPI1 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x02008000 0x4000>;
|
|
interrupts = <0 31 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi@0200c000 { /* eCSPI2 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x0200c000 0x4000>;
|
|
interrupts = <0 32 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi@02010000 { /* eCSPI3 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x02010000 0x4000>;
|
|
interrupts = <0 33 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi@02014000 { /* eCSPI4 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x02014000 0x4000>;
|
|
interrupts = <0 34 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi@02018000 { /* eCSPI5 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x02018000 0x4000>;
|
|
interrupts = <0 35 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@02020000 {
|
|
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
|
reg = <0x02020000 0x4000>;
|
|
interrupts = <0 26 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
esai@02024000 {
|
|
reg = <0x02024000 0x4000>;
|
|
interrupts = <0 51 0x04>;
|
|
};
|
|
|
|
ssi1: ssi@02028000 {
|
|
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
|
|
reg = <0x02028000 0x4000>;
|
|
interrupts = <0 46 0x04>;
|
|
fsl,fifo-depth = <15>;
|
|
fsl,ssi-dma-events = <38 37>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssi2: ssi@0202c000 {
|
|
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
|
|
reg = <0x0202c000 0x4000>;
|
|
interrupts = <0 47 0x04>;
|
|
fsl,fifo-depth = <15>;
|
|
fsl,ssi-dma-events = <42 41>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssi3: ssi@02030000 {
|
|
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
|
|
reg = <0x02030000 0x4000>;
|
|
interrupts = <0 48 0x04>;
|
|
fsl,fifo-depth = <15>;
|
|
fsl,ssi-dma-events = <46 45>;
|
|
status = "disabled";
|
|
};
|
|
|
|
asrc@02034000 {
|
|
reg = <0x02034000 0x4000>;
|
|
interrupts = <0 50 0x04>;
|
|
};
|
|
|
|
spba@0203c000 {
|
|
reg = <0x0203c000 0x4000>;
|
|
};
|
|
};
|
|
|
|
vpu@02040000 {
|
|
reg = <0x02040000 0x3c000>;
|
|
interrupts = <0 3 0x04 0 12 0x04>;
|
|
};
|
|
|
|
aipstz@0207c000 { /* AIPSTZ1 */
|
|
reg = <0x0207c000 0x4000>;
|
|
};
|
|
|
|
pwm@02080000 { /* PWM1 */
|
|
reg = <0x02080000 0x4000>;
|
|
interrupts = <0 83 0x04>;
|
|
};
|
|
|
|
pwm@02084000 { /* PWM2 */
|
|
reg = <0x02084000 0x4000>;
|
|
interrupts = <0 84 0x04>;
|
|
};
|
|
|
|
pwm@02088000 { /* PWM3 */
|
|
reg = <0x02088000 0x4000>;
|
|
interrupts = <0 85 0x04>;
|
|
};
|
|
|
|
pwm@0208c000 { /* PWM4 */
|
|
reg = <0x0208c000 0x4000>;
|
|
interrupts = <0 86 0x04>;
|
|
};
|
|
|
|
flexcan@02090000 { /* CAN1 */
|
|
reg = <0x02090000 0x4000>;
|
|
interrupts = <0 110 0x04>;
|
|
};
|
|
|
|
flexcan@02094000 { /* CAN2 */
|
|
reg = <0x02094000 0x4000>;
|
|
interrupts = <0 111 0x04>;
|
|
};
|
|
|
|
gpt@02098000 {
|
|
compatible = "fsl,imx6q-gpt";
|
|
reg = <0x02098000 0x4000>;
|
|
interrupts = <0 55 0x04>;
|
|
};
|
|
|
|
gpio1: gpio@0209c000 {
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
|
reg = <0x0209c000 0x4000>;
|
|
interrupts = <0 66 0x04 0 67 0x04>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio@020a0000 {
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020a0000 0x4000>;
|
|
interrupts = <0 68 0x04 0 69 0x04>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio@020a4000 {
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020a4000 0x4000>;
|
|
interrupts = <0 70 0x04 0 71 0x04>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio4: gpio@020a8000 {
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020a8000 0x4000>;
|
|
interrupts = <0 72 0x04 0 73 0x04>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio5: gpio@020ac000 {
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020ac000 0x4000>;
|
|
interrupts = <0 74 0x04 0 75 0x04>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio6: gpio@020b0000 {
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020b0000 0x4000>;
|
|
interrupts = <0 76 0x04 0 77 0x04>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio7: gpio@020b4000 {
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020b4000 0x4000>;
|
|
interrupts = <0 78 0x04 0 79 0x04>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
kpp@020b8000 {
|
|
reg = <0x020b8000 0x4000>;
|
|
interrupts = <0 82 0x04>;
|
|
};
|
|
|
|
wdog@020bc000 { /* WDOG1 */
|
|
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
|
reg = <0x020bc000 0x4000>;
|
|
interrupts = <0 80 0x04>;
|
|
};
|
|
|
|
wdog@020c0000 { /* WDOG2 */
|
|
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
|
reg = <0x020c0000 0x4000>;
|
|
interrupts = <0 81 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ccm@020c4000 {
|
|
compatible = "fsl,imx6q-ccm";
|
|
reg = <0x020c4000 0x4000>;
|
|
interrupts = <0 87 0x04 0 88 0x04>;
|
|
};
|
|
|
|
anatop@020c8000 {
|
|
compatible = "fsl,imx6q-anatop";
|
|
reg = <0x020c8000 0x1000>;
|
|
interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
|
|
|
|
regulator-1p1@110 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vdd1p1";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1375000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x110>;
|
|
anatop-vol-bit-shift = <8>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-min-bit-val = <4>;
|
|
anatop-min-voltage = <800000>;
|
|
anatop-max-voltage = <1375000>;
|
|
};
|
|
|
|
regulator-3p0@120 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vdd3p0";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <3150000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x120>;
|
|
anatop-vol-bit-shift = <8>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-min-bit-val = <0>;
|
|
anatop-min-voltage = <2625000>;
|
|
anatop-max-voltage = <3400000>;
|
|
};
|
|
|
|
regulator-2p5@130 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vdd2p5";
|
|
regulator-min-microvolt = <2000000>;
|
|
regulator-max-microvolt = <2750000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x130>;
|
|
anatop-vol-bit-shift = <8>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-min-bit-val = <0>;
|
|
anatop-min-voltage = <2000000>;
|
|
anatop-max-voltage = <2750000>;
|
|
};
|
|
|
|
regulator-vddcore@140 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "cpu";
|
|
regulator-min-microvolt = <725000>;
|
|
regulator-max-microvolt = <1450000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x140>;
|
|
anatop-vol-bit-shift = <0>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-min-bit-val = <1>;
|
|
anatop-min-voltage = <725000>;
|
|
anatop-max-voltage = <1450000>;
|
|
};
|
|
|
|
regulator-vddpu@140 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vddpu";
|
|
regulator-min-microvolt = <725000>;
|
|
regulator-max-microvolt = <1450000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x140>;
|
|
anatop-vol-bit-shift = <9>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-min-bit-val = <1>;
|
|
anatop-min-voltage = <725000>;
|
|
anatop-max-voltage = <1450000>;
|
|
};
|
|
|
|
regulator-vddsoc@140 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vddsoc";
|
|
regulator-min-microvolt = <725000>;
|
|
regulator-max-microvolt = <1450000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x140>;
|
|
anatop-vol-bit-shift = <18>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-min-bit-val = <1>;
|
|
anatop-min-voltage = <725000>;
|
|
anatop-max-voltage = <1450000>;
|
|
};
|
|
};
|
|
|
|
usbphy1: usbphy@020c9000 {
|
|
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
|
|
reg = <0x020c9000 0x1000>;
|
|
interrupts = <0 44 0x04>;
|
|
};
|
|
|
|
usbphy2: usbphy@020ca000 {
|
|
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
|
|
reg = <0x020ca000 0x1000>;
|
|
interrupts = <0 45 0x04>;
|
|
};
|
|
|
|
snvs@020cc000 {
|
|
reg = <0x020cc000 0x4000>;
|
|
interrupts = <0 19 0x04 0 20 0x04>;
|
|
};
|
|
|
|
epit@020d0000 { /* EPIT1 */
|
|
reg = <0x020d0000 0x4000>;
|
|
interrupts = <0 56 0x04>;
|
|
};
|
|
|
|
epit@020d4000 { /* EPIT2 */
|
|
reg = <0x020d4000 0x4000>;
|
|
interrupts = <0 57 0x04>;
|
|
};
|
|
|
|
src@020d8000 {
|
|
compatible = "fsl,imx6q-src";
|
|
reg = <0x020d8000 0x4000>;
|
|
interrupts = <0 91 0x04 0 96 0x04>;
|
|
};
|
|
|
|
gpc@020dc000 {
|
|
compatible = "fsl,imx6q-gpc";
|
|
reg = <0x020dc000 0x4000>;
|
|
interrupts = <0 89 0x04 0 90 0x04>;
|
|
};
|
|
|
|
iomuxc@020e0000 {
|
|
compatible = "fsl,imx6q-iomuxc";
|
|
reg = <0x020e0000 0x4000>;
|
|
|
|
/* shared pinctrl settings */
|
|
audmux {
|
|
pinctrl_audmux_1: audmux-1 {
|
|
fsl,pins = <
|
|
18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
|
|
1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
|
|
11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
|
|
3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
|
|
>;
|
|
};
|
|
};
|
|
|
|
gpmi-nand {
|
|
pinctrl_gpmi_nand_1: gpmi-nand-1 {
|
|
fsl,pins = <
|
|
1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
|
|
1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
|
|
1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
|
|
1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
|
|
1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
|
|
1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
|
|
1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
|
|
1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
|
|
1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
|
|
1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
|
|
1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
|
|
1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
|
|
1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
|
|
1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
|
|
1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
|
|
1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
|
|
1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
|
|
1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
|
|
1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
|
|
>;
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
pinctrl_i2c1_1: i2c1grp-1 {
|
|
fsl,pins = <
|
|
137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
|
|
196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
|
|
>;
|
|
};
|
|
};
|
|
|
|
uart2 {
|
|
pinctrl_uart2_1: uart2grp-1 {
|
|
fsl,pins = <
|
|
183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
|
|
191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
|
|
>;
|
|
};
|
|
};
|
|
|
|
usdhc3 {
|
|
pinctrl_usdhc3_1: usdhc3grp-1 {
|
|
fsl,pins = <
|
|
1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
|
|
1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
|
|
1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
|
|
1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
|
|
1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
|
|
1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
|
|
1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
|
|
1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
|
|
1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
|
|
1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
|
|
>;
|
|
};
|
|
};
|
|
|
|
usdhc4 {
|
|
pinctrl_usdhc4_1: usdhc4grp-1 {
|
|
fsl,pins = <
|
|
1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
|
|
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
|
|
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
|
|
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
|
|
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
|
|
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
|
|
1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
|
|
1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
|
|
1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
|
|
1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
|
|
>;
|
|
};
|
|
};
|
|
|
|
ecspi1 {
|
|
pinctrl_ecspi1_1: ecspi1grp-1 {
|
|
fsl,pins = <
|
|
101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
|
|
109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
|
|
94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
|
|
>;
|
|
};
|
|
};
|
|
};
|
|
|
|
dcic@020e4000 { /* DCIC1 */
|
|
reg = <0x020e4000 0x4000>;
|
|
interrupts = <0 124 0x04>;
|
|
};
|
|
|
|
dcic@020e8000 { /* DCIC2 */
|
|
reg = <0x020e8000 0x4000>;
|
|
interrupts = <0 125 0x04>;
|
|
};
|
|
|
|
sdma@020ec000 {
|
|
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
|
|
reg = <0x020ec000 0x4000>;
|
|
interrupts = <0 2 0x04>;
|
|
};
|
|
};
|
|
|
|
aips-bus@02100000 { /* AIPS2 */
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x02100000 0x100000>;
|
|
ranges;
|
|
|
|
caam@02100000 {
|
|
reg = <0x02100000 0x40000>;
|
|
interrupts = <0 105 0x04 0 106 0x04>;
|
|
};
|
|
|
|
aipstz@0217c000 { /* AIPSTZ2 */
|
|
reg = <0x0217c000 0x4000>;
|
|
};
|
|
|
|
usb@02184000 { /* USB OTG */
|
|
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
|
reg = <0x02184000 0x200>;
|
|
interrupts = <0 43 0x04>;
|
|
fsl,usbphy = <&usbphy1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@02184200 { /* USB1 */
|
|
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
|
reg = <0x02184200 0x200>;
|
|
interrupts = <0 40 0x04>;
|
|
fsl,usbphy = <&usbphy2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@02184400 { /* USB2 */
|
|
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
|
reg = <0x02184400 0x200>;
|
|
interrupts = <0 41 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@02184600 { /* USB3 */
|
|
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
|
reg = <0x02184600 0x200>;
|
|
interrupts = <0 42 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ethernet@02188000 {
|
|
compatible = "fsl,imx6q-fec";
|
|
reg = <0x02188000 0x4000>;
|
|
interrupts = <0 118 0x04 0 119 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mlb@0218c000 {
|
|
reg = <0x0218c000 0x4000>;
|
|
interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
|
|
};
|
|
|
|
usdhc@02190000 { /* uSDHC1 */
|
|
compatible = "fsl,imx6q-usdhc";
|
|
reg = <0x02190000 0x4000>;
|
|
interrupts = <0 22 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc@02194000 { /* uSDHC2 */
|
|
compatible = "fsl,imx6q-usdhc";
|
|
reg = <0x02194000 0x4000>;
|
|
interrupts = <0 23 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc@02198000 { /* uSDHC3 */
|
|
compatible = "fsl,imx6q-usdhc";
|
|
reg = <0x02198000 0x4000>;
|
|
interrupts = <0 24 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc@0219c000 { /* uSDHC4 */
|
|
compatible = "fsl,imx6q-usdhc";
|
|
reg = <0x0219c000 0x4000>;
|
|
interrupts = <0 25 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@021a0000 { /* I2C1 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
|
|
reg = <0x021a0000 0x4000>;
|
|
interrupts = <0 36 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@021a4000 { /* I2C2 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
|
|
reg = <0x021a4000 0x4000>;
|
|
interrupts = <0 37 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@021a8000 { /* I2C3 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
|
|
reg = <0x021a8000 0x4000>;
|
|
interrupts = <0 38 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
romcp@021ac000 {
|
|
reg = <0x021ac000 0x4000>;
|
|
};
|
|
|
|
mmdc@021b0000 { /* MMDC0 */
|
|
compatible = "fsl,imx6q-mmdc";
|
|
reg = <0x021b0000 0x4000>;
|
|
};
|
|
|
|
mmdc@021b4000 { /* MMDC1 */
|
|
reg = <0x021b4000 0x4000>;
|
|
};
|
|
|
|
weim@021b8000 {
|
|
reg = <0x021b8000 0x4000>;
|
|
interrupts = <0 14 0x04>;
|
|
};
|
|
|
|
ocotp@021bc000 {
|
|
reg = <0x021bc000 0x4000>;
|
|
};
|
|
|
|
ocotp@021c0000 {
|
|
reg = <0x021c0000 0x4000>;
|
|
interrupts = <0 21 0x04>;
|
|
};
|
|
|
|
tzasc@021d0000 { /* TZASC1 */
|
|
reg = <0x021d0000 0x4000>;
|
|
interrupts = <0 108 0x04>;
|
|
};
|
|
|
|
tzasc@021d4000 { /* TZASC2 */
|
|
reg = <0x021d4000 0x4000>;
|
|
interrupts = <0 109 0x04>;
|
|
};
|
|
|
|
audmux@021d8000 {
|
|
compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
|
|
reg = <0x021d8000 0x4000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mipi@021dc000 { /* MIPI-CSI */
|
|
reg = <0x021dc000 0x4000>;
|
|
};
|
|
|
|
mipi@021e0000 { /* MIPI-DSI */
|
|
reg = <0x021e0000 0x4000>;
|
|
};
|
|
|
|
vdoa@021e4000 {
|
|
reg = <0x021e4000 0x4000>;
|
|
interrupts = <0 18 0x04>;
|
|
};
|
|
|
|
uart2: serial@021e8000 {
|
|
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
|
reg = <0x021e8000 0x4000>;
|
|
interrupts = <0 27 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@021ec000 {
|
|
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
|
reg = <0x021ec000 0x4000>;
|
|
interrupts = <0 28 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@021f0000 {
|
|
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
|
reg = <0x021f0000 0x4000>;
|
|
interrupts = <0 29 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@021f4000 {
|
|
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
|
reg = <0x021f4000 0x4000>;
|
|
interrupts = <0 30 0x04>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|