Florian Fainelli e1c96c8620 MIPS: BCM63xx: Remove BCM6345 hacks to read base boot address ... Though BCM6345 does not technically have the same MPI register layout than the other SoCs, reading the chip-select registers is done the same way, and particularly for chip-select 0, which is the boot flash. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2011-12-07 22:03:04 +00:00
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bcm63xx_board.h
bcm63xx_clk.h
bcm63xx_cpu.h	MIPS: BCM63xx: Remove BCM6345 hacks to read base boot address	2011-12-07 22:03:04 +00:00
bcm63xx_cs.h
bcm63xx_dev_dsp.h
bcm63xx_dev_enet.h
bcm63xx_dev_pci.h
bcm63xx_dev_pcmcia.h	MIPS: BCM63xx: Add PCMCIA & Cardbus support.	2009-09-30 21:47:01 +02:00
bcm63xx_dev_uart.h	MIPS: BCM63xx: Add support for second uart.	2010-04-12 17:26:18 +01:00
bcm63xx_gpio.h	MIPS: BCM63XX: Add support for bcm6368 CPU.	2011-12-07 22:03:04 +00:00
bcm63xx_io.h	MIPS: BCM63XX: Introduce bcm_readq & bcm_writeq.	2011-12-07 22:03:03 +00:00
bcm63xx_irq.h	MIPS: BCM63XX: Prepare irq code to handle different external irq hardware implementation.	2011-12-07 22:03:03 +00:00
bcm63xx_regs.h	MIPS: BCM63xx: Fix SDRAM size computation for BCM6345	2011-12-07 22:03:04 +00:00
bcm63xx_timer.h
bcm963xx_tag.h	MIPS: bcm63xx: Fix header_crc comment in bcm963xx_tag.h	2011-05-10 18:15:24 +01:00
board_bcm963xx.h	MIPS: BCM63xx: Add support for second uart.	2010-04-12 17:26:18 +01:00
cpu-feature-overrides.h	MIPS: BCM63xx: Fix typo in cpu-feature-overrides file.	2010-04-12 17:26:18 +01:00
gpio.h	MIPS: AR7, BCM63xx: fix gpio_to_irq() return value	2010-07-05 17:17:26 +01:00
ioremap.h	MIPS: BCM63XX: Add support for bcm6368 CPU.	2011-12-07 22:03:04 +00:00
irq.h	MIPS: BCM63XX: Prepare irq code to handle different external irq hardware implementation.	2011-12-07 22:03:03 +00:00
spaces.h	MIPS: Move FIXADDR_TOP into spaces.h	2011-07-25 17:26:53 +01:00
war.h