052af915d8
EDC counts are related to instance and se. They are not the same for different type of EDC. EDC clearing are changed to base on individual EDC's instance and SE number. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
76 lines
2.5 KiB
C
76 lines
2.5 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __SOC15_H__
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#define __SOC15_H__
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#include "nbio_v6_1.h"
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#include "nbio_v7_0.h"
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#include "nbio_v7_4.h"
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#define SOC15_FLUSH_GPU_TLB_NUM_WREG 4
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#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT 1
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extern const struct amd_ip_funcs soc15_common_ip_funcs;
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struct soc15_reg_golden {
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u32 hwip;
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u32 instance;
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u32 segment;
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u32 reg;
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u32 and_mask;
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u32 or_mask;
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};
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struct soc15_reg_entry {
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uint32_t hwip;
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uint32_t inst;
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uint32_t seg;
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uint32_t reg_offset;
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uint32_t reg_value;
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uint32_t se_num;
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uint32_t instance;
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};
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#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
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#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
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#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
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{ ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
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void soc15_grbm_select(struct amdgpu_device *adev,
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u32 me, u32 pipe, u32 queue, u32 vmid);
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int soc15_set_ip_blocks(struct amdgpu_device *adev);
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void soc15_program_register_sequence(struct amdgpu_device *adev,
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const struct soc15_reg_golden *registers,
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const u32 array_size);
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int vega10_reg_base_init(struct amdgpu_device *adev);
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int vega20_reg_base_init(struct amdgpu_device *adev);
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void vega10_doorbell_index_init(struct amdgpu_device *adev);
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void vega20_doorbell_index_init(struct amdgpu_device *adev);
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#endif
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