forked from Minki/linux
af170c5061
Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Michael Kerrisk <mtk.manpages@gmail.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Dave Jones <davej@redhat.com>
268 lines
7.0 KiB
C
268 lines
7.0 KiB
C
#ifndef _ASM_X86_MSR_H
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#define _ASM_X86_MSR_H
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#include <uapi/asm/msr.h>
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#ifndef __ASSEMBLY__
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#include <asm/asm.h>
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#include <asm/errno.h>
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#include <asm/cpumask.h>
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struct msr {
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union {
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struct {
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u32 l;
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u32 h;
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};
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u64 q;
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};
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};
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struct msr_info {
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u32 msr_no;
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struct msr reg;
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struct msr *msrs;
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int err;
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};
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struct msr_regs_info {
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u32 *regs;
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int err;
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};
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static inline unsigned long long native_read_tscp(unsigned int *aux)
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{
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unsigned long low, high;
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asm volatile(".byte 0x0f,0x01,0xf9"
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: "=a" (low), "=d" (high), "=c" (*aux));
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return low | ((u64)high << 32);
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}
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/*
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* both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A"
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* constraint has different meanings. For i386, "A" means exactly
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* edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
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* it means rax *or* rdx.
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*/
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#ifdef CONFIG_X86_64
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#define DECLARE_ARGS(val, low, high) unsigned low, high
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#define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32))
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#define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high)
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#define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high)
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#else
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#define DECLARE_ARGS(val, low, high) unsigned long long val
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#define EAX_EDX_VAL(val, low, high) (val)
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#define EAX_EDX_ARGS(val, low, high) "A" (val)
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#define EAX_EDX_RET(val, low, high) "=A" (val)
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#endif
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static inline unsigned long long native_read_msr(unsigned int msr)
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{
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DECLARE_ARGS(val, low, high);
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asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr));
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return EAX_EDX_VAL(val, low, high);
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}
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static inline unsigned long long native_read_msr_safe(unsigned int msr,
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int *err)
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{
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DECLARE_ARGS(val, low, high);
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asm volatile("2: rdmsr ; xor %[err],%[err]\n"
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"1:\n\t"
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".section .fixup,\"ax\"\n\t"
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"3: mov %[fault],%[err] ; jmp 1b\n\t"
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".previous\n\t"
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_ASM_EXTABLE(2b, 3b)
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: [err] "=r" (*err), EAX_EDX_RET(val, low, high)
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: "c" (msr), [fault] "i" (-EIO));
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return EAX_EDX_VAL(val, low, high);
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}
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static inline void native_write_msr(unsigned int msr,
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unsigned low, unsigned high)
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{
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asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory");
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}
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/* Can be uninlined because referenced by paravirt */
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notrace static inline int native_write_msr_safe(unsigned int msr,
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unsigned low, unsigned high)
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{
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int err;
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asm volatile("2: wrmsr ; xor %[err],%[err]\n"
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"1:\n\t"
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".section .fixup,\"ax\"\n\t"
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"3: mov %[fault],%[err] ; jmp 1b\n\t"
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".previous\n\t"
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_ASM_EXTABLE(2b, 3b)
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: [err] "=a" (err)
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: "c" (msr), "0" (low), "d" (high),
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[fault] "i" (-EIO)
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: "memory");
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return err;
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}
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extern unsigned long long native_read_tsc(void);
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extern int rdmsr_safe_regs(u32 regs[8]);
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extern int wrmsr_safe_regs(u32 regs[8]);
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static __always_inline unsigned long long __native_read_tsc(void)
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{
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DECLARE_ARGS(val, low, high);
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asm volatile("rdtsc" : EAX_EDX_RET(val, low, high));
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return EAX_EDX_VAL(val, low, high);
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}
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static inline unsigned long long native_read_pmc(int counter)
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{
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DECLARE_ARGS(val, low, high);
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asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
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return EAX_EDX_VAL(val, low, high);
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}
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#include <linux/errno.h>
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/*
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* Access to machine-specific registers (available on 586 and better only)
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* Note: the rd* operations modify the parameters directly (without using
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* pointer indirection), this allows gcc to optimize better
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*/
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#define rdmsr(msr, val1, val2) \
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do { \
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u64 __val = native_read_msr((msr)); \
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(void)((val1) = (u32)__val); \
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(void)((val2) = (u32)(__val >> 32)); \
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} while (0)
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static inline void wrmsr(unsigned msr, unsigned low, unsigned high)
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{
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native_write_msr(msr, low, high);
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}
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#define rdmsrl(msr, val) \
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((val) = native_read_msr((msr)))
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#define wrmsrl(msr, val) \
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native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32))
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/* wrmsr with exception handling */
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static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high)
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{
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return native_write_msr_safe(msr, low, high);
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}
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/* rdmsr with exception handling */
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#define rdmsr_safe(msr, p1, p2) \
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({ \
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int __err; \
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u64 __val = native_read_msr_safe((msr), &__err); \
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(*p1) = (u32)__val; \
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(*p2) = (u32)(__val >> 32); \
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__err; \
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})
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static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
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{
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int err;
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*p = native_read_msr_safe(msr, &err);
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return err;
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}
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#define rdtscl(low) \
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((low) = (u32)__native_read_tsc())
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#define rdtscll(val) \
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((val) = __native_read_tsc())
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#define rdpmc(counter, low, high) \
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do { \
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u64 _l = native_read_pmc((counter)); \
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(low) = (u32)_l; \
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(high) = (u32)(_l >> 32); \
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} while (0)
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#define rdpmcl(counter, val) ((val) = native_read_pmc(counter))
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#define rdtscp(low, high, aux) \
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do { \
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unsigned long long _val = native_read_tscp(&(aux)); \
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(low) = (u32)_val; \
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(high) = (u32)(_val >> 32); \
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} while (0)
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#define rdtscpll(val, aux) (val) = native_read_tscp(&(aux))
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#endif /* !CONFIG_PARAVIRT */
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#define wrmsrl_safe(msr, val) wrmsr_safe((msr), (u32)(val), \
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(u32)((val) >> 32))
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#define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2))
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#define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
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struct msr *msrs_alloc(void);
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void msrs_free(struct msr *msrs);
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#ifdef CONFIG_SMP
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int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
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int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
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void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
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void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
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int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
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int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
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int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
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int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
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#else /* CONFIG_SMP */
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static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
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{
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rdmsr(msr_no, *l, *h);
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return 0;
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}
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static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
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{
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wrmsr(msr_no, l, h);
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return 0;
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}
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static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no,
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struct msr *msrs)
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{
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rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h));
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}
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static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no,
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struct msr *msrs)
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{
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wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h);
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}
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static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
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u32 *l, u32 *h)
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{
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return rdmsr_safe(msr_no, l, h);
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}
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static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
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{
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return wrmsr_safe(msr_no, l, h);
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}
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static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
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{
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return rdmsr_safe_regs(regs);
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}
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static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
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{
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return wrmsr_safe_regs(regs);
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}
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#endif /* CONFIG_SMP */
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_X86_MSR_H */
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