forked from Minki/linux
dc4e96ce2d
The max depth supported by T3 is 64K entries. This fixes a bug
introduced in commit 9918b28d ("RDMA/cxgb3: Increase the max CQ
depth") that causes stalls and possibly crashes in large MPI clusters.
Signed-off-by: Steve Wise <swise@opengridcomputing.com>
Cc: <stable@kernel.org>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
212 lines
7.3 KiB
C
212 lines
7.3 KiB
C
/*
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* Copyright (c) 2006 Chelsio, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __CXIO_HAL_H__
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#define __CXIO_HAL_H__
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/kfifo.h>
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#include "t3_cpl.h"
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#include "t3cdev.h"
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#include "cxgb3_ctl_defs.h"
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#include "cxio_wr.h"
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#define T3_CTRL_QP_ID FW_RI_SGEEC_START
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#define T3_CTL_QP_TID FW_RI_TID_START
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#define T3_CTRL_QP_SIZE_LOG2 8
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#define T3_CTRL_CQ_ID 0
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#define T3_MAX_NUM_RI (1<<15)
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#define T3_MAX_NUM_QP (1<<15)
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#define T3_MAX_NUM_CQ (1<<15)
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#define T3_MAX_NUM_PD (1<<15)
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#define T3_MAX_PBL_SIZE 256
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#define T3_MAX_RQ_SIZE 1024
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#define T3_MAX_QP_DEPTH (T3_MAX_RQ_SIZE-1)
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#define T3_MAX_CQ_DEPTH 65536
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#define T3_MAX_NUM_STAG (1<<15)
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#define T3_MAX_MR_SIZE 0x100000000ULL
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#define T3_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
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#define T3_STAG_UNSET 0xffffffff
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#define T3_MAX_DEV_NAME_LEN 32
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#define CXIO_FW_MAJ 7
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struct cxio_hal_ctrl_qp {
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u32 wptr;
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u32 rptr;
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struct mutex lock; /* for the wtpr, can sleep */
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wait_queue_head_t waitq;/* wait for RspQ/CQE msg */
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union t3_wr *workq; /* the work request queue */
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dma_addr_t dma_addr; /* pci bus address of the workq */
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DEFINE_DMA_UNMAP_ADDR(mapping);
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void __iomem *doorbell;
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};
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struct cxio_hal_resource {
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struct kfifo tpt_fifo;
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spinlock_t tpt_fifo_lock;
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struct kfifo qpid_fifo;
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spinlock_t qpid_fifo_lock;
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struct kfifo cqid_fifo;
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spinlock_t cqid_fifo_lock;
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struct kfifo pdid_fifo;
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spinlock_t pdid_fifo_lock;
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};
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struct cxio_qpid_list {
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struct list_head entry;
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u32 qpid;
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};
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struct cxio_ucontext {
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struct list_head qpids;
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struct mutex lock;
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};
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struct cxio_rdev {
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char dev_name[T3_MAX_DEV_NAME_LEN];
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struct t3cdev *t3cdev_p;
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struct rdma_info rnic_info;
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struct adap_ports port_info;
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struct cxio_hal_resource *rscp;
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struct cxio_hal_ctrl_qp ctrl_qp;
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void *ulp;
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unsigned long qpshift;
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u32 qpnr;
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u32 qpmask;
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struct cxio_ucontext uctx;
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struct gen_pool *pbl_pool;
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struct gen_pool *rqt_pool;
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struct list_head entry;
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struct ch_embedded_info fw_info;
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u32 flags;
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#define CXIO_ERROR_FATAL 1
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};
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static inline int cxio_fatal_error(struct cxio_rdev *rdev_p)
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{
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return rdev_p->flags & CXIO_ERROR_FATAL;
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}
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static inline int cxio_num_stags(struct cxio_rdev *rdev_p)
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{
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return min((int)T3_MAX_NUM_STAG, (int)((rdev_p->rnic_info.tpt_top - rdev_p->rnic_info.tpt_base) >> 5));
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}
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typedef void (*cxio_hal_ev_callback_func_t) (struct cxio_rdev * rdev_p,
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struct sk_buff * skb);
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#define RSPQ_CQID(rsp) (be32_to_cpu(rsp->cq_ptrid) & 0xffff)
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#define RSPQ_CQPTR(rsp) ((be32_to_cpu(rsp->cq_ptrid) >> 16) & 0xffff)
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#define RSPQ_GENBIT(rsp) ((be32_to_cpu(rsp->flags) >> 16) & 1)
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#define RSPQ_OVERFLOW(rsp) ((be32_to_cpu(rsp->flags) >> 17) & 1)
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#define RSPQ_AN(rsp) ((be32_to_cpu(rsp->flags) >> 18) & 1)
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#define RSPQ_SE(rsp) ((be32_to_cpu(rsp->flags) >> 19) & 1)
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#define RSPQ_NOTIFY(rsp) ((be32_to_cpu(rsp->flags) >> 20) & 1)
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#define RSPQ_CQBRANCH(rsp) ((be32_to_cpu(rsp->flags) >> 21) & 1)
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#define RSPQ_CREDIT_THRESH(rsp) ((be32_to_cpu(rsp->flags) >> 22) & 1)
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struct respQ_msg_t {
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__be32 flags; /* flit 0 */
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__be32 cq_ptrid;
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__be64 rsvd; /* flit 1 */
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struct t3_cqe cqe; /* flits 2-3 */
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};
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enum t3_cq_opcode {
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CQ_ARM_AN = 0x2,
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CQ_ARM_SE = 0x6,
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CQ_FORCE_AN = 0x3,
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CQ_CREDIT_UPDATE = 0x7
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};
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int cxio_rdev_open(struct cxio_rdev *rdev);
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void cxio_rdev_close(struct cxio_rdev *rdev);
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int cxio_hal_cq_op(struct cxio_rdev *rdev, struct t3_cq *cq,
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enum t3_cq_opcode op, u32 credit);
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int cxio_create_cq(struct cxio_rdev *rdev, struct t3_cq *cq, int kernel);
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int cxio_destroy_cq(struct cxio_rdev *rdev, struct t3_cq *cq);
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int cxio_resize_cq(struct cxio_rdev *rdev, struct t3_cq *cq);
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void cxio_release_ucontext(struct cxio_rdev *rdev, struct cxio_ucontext *uctx);
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void cxio_init_ucontext(struct cxio_rdev *rdev, struct cxio_ucontext *uctx);
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int cxio_create_qp(struct cxio_rdev *rdev, u32 kernel_domain, struct t3_wq *wq,
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struct cxio_ucontext *uctx);
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int cxio_destroy_qp(struct cxio_rdev *rdev, struct t3_wq *wq,
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struct cxio_ucontext *uctx);
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int cxio_peek_cq(struct t3_wq *wr, struct t3_cq *cq, int opcode);
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int cxio_write_pbl(struct cxio_rdev *rdev_p, __be64 *pbl,
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u32 pbl_addr, u32 pbl_size);
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int cxio_register_phys_mem(struct cxio_rdev *rdev, u32 * stag, u32 pdid,
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enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
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u8 page_size, u32 pbl_size, u32 pbl_addr);
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int cxio_reregister_phys_mem(struct cxio_rdev *rdev, u32 * stag, u32 pdid,
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enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
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u8 page_size, u32 pbl_size, u32 pbl_addr);
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int cxio_dereg_mem(struct cxio_rdev *rdev, u32 stag, u32 pbl_size,
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u32 pbl_addr);
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int cxio_allocate_window(struct cxio_rdev *rdev, u32 * stag, u32 pdid);
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int cxio_allocate_stag(struct cxio_rdev *rdev, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr);
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int cxio_deallocate_window(struct cxio_rdev *rdev, u32 stag);
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int cxio_rdma_init(struct cxio_rdev *rdev, struct t3_rdma_init_attr *attr);
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void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb);
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void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb);
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u32 cxio_hal_get_pdid(struct cxio_hal_resource *rscp);
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void cxio_hal_put_pdid(struct cxio_hal_resource *rscp, u32 pdid);
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int __init cxio_hal_init(void);
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void __exit cxio_hal_exit(void);
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int cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count);
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int cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count);
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void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count);
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void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count);
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void cxio_flush_hw_cq(struct t3_cq *cq);
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int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
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u8 *cqe_flushed, u64 *cookie, u32 *credit);
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int iwch_cxgb3_ofld_send(struct t3cdev *tdev, struct sk_buff *skb);
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#define MOD "iw_cxgb3: "
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#define PDBG(fmt, args...) pr_debug(MOD fmt, ## args)
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#ifdef DEBUG
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void cxio_dump_tpt(struct cxio_rdev *rev, u32 stag);
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void cxio_dump_pbl(struct cxio_rdev *rev, u32 pbl_addr, uint len, u8 shift);
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void cxio_dump_wqe(union t3_wr *wqe);
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void cxio_dump_wce(struct t3_cqe *wce);
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void cxio_dump_rqt(struct cxio_rdev *rdev, u32 hwtid, int nents);
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void cxio_dump_tcb(struct cxio_rdev *rdev, u32 hwtid);
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#endif
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#endif
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