James Hogan e06a1548f3 MIPS: Add defs & probing of BadInstr[P] registers ... The optional CP0_BadInstr and CP0_BadInstrP registers are written with the encoding of the instruction that caused a synchronous exception to occur, and the prior branch instruction if in a delay slot. These will be useful for instruction emulation in KVM, and especially for VZ support where reading guest virtual memory is a bit more awkward. Add CPU option numbers and cpu_has_* definitions to indicate the presence of each registers, and add code to probe for them using bits in the CP0_Config3 register. [ralf@linux-mips.org: resolve merge conflict.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13224/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2016-05-13 15:30:25 +02:00
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asm	MIPS: Add defs & probing of BadInstr[P] registers	2016-05-13 15:30:25 +02:00
uapi/asm	MIPS: inst: Declare fsel_op for sel.fmt instruction	2016-05-13 14:02:21 +02:00