forked from Minki/linux
e045fa29e8
When a driver enables MSI-X, msix_program_entries() reads the MSI-X Vector Control register for each vector and saves it in desc->masked. Each register is 32 bits and bit 0 is the actual Mask bit. When we restored these registers during resume, we previously set the Mask bit if *any* bit in desc->masked was set instead of when the Mask bit itself was set: pci_restore_state pci_restore_msi_state __pci_restore_msix_state for_each_pci_msi_entry msix_mask_irq(entry, entry->masked) <-- entire u32 word __pci_msix_desc_mask_irq(desc, flag) mask_bits = desc->masked & ~PCI_MSIX_ENTRY_CTRL_MASKBIT if (flag) <-- testing entire u32, not just bit 0 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT writel(mask_bits, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL) This means that after resume, MSI-X vectors were masked when they shouldn't be, which leads to timeouts like this: nvme nvme0: I/O 978 QID 3 timeout, completion polled On resume, set the Mask bit only when the saved Mask bit from suspend was set. This should remove the need for |
||
---|---|---|
.. | ||
controller | ||
endpoint | ||
hotplug | ||
pcie | ||
switch | ||
access.c | ||
ats.c | ||
bus.c | ||
ecam.c | ||
host-bridge.c | ||
iov.c | ||
irq.c | ||
Kconfig | ||
Makefile | ||
mmap.c | ||
msi.c | ||
of.c | ||
p2pdma.c | ||
pci-acpi.c | ||
pci-bridge-emul.c | ||
pci-bridge-emul.h | ||
pci-driver.c | ||
pci-label.c | ||
pci-mid.c | ||
pci-pf-stub.c | ||
pci-stub.c | ||
pci-sysfs.c | ||
pci.c | ||
pci.h | ||
probe.c | ||
proc.c | ||
quirks.c | ||
remove.c | ||
rom.c | ||
search.c | ||
setup-bus.c | ||
setup-irq.c | ||
setup-res.c | ||
slot.c | ||
syscall.c | ||
vc.c | ||
vpd.c | ||
xen-pcifront.c |