forked from Minki/linux
dfc94d1b21
In preparation for GIC IRQ domain support, assign a GIC IRQ base that does not overlap with the CPU IRQs. Note that this breaks SEAD-3 when the GIC is in EIC mode, though I'm not convinced it was working before either. It will be fixed in the following patches. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7813/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
20 lines
580 B
C
20 lines
580 B
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved.
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* Douglas Leung <douglas@mips.com>
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* Steven J. Hill <sjhill@mips.com>
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*/
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#ifndef _MIPS_SEAD3INT_H
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#define _MIPS_SEAD3INT_H
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/* SEAD-3 GIC address space definitions. */
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#define GIC_BASE_ADDR 0x1b1c0000
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#define GIC_ADDRSPACE_SZ (128 * 1024)
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#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
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#endif /* !(_MIPS_SEAD3INT_H) */
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