forked from Minki/linux
df5d6ecf81
Support for TLB reservation (or TLB Write Conditional) and Paired MAS registers are optional for a processor implementation so we handle them via MMU feature sections. We currently only used paired MAS registers to access the full RPN + perm bits that are kept in MAS7||MAS3. We assume that if an implementation has hardware page table at this time it also implements in TLB reservations. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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boot | ||
configs | ||
include/asm | ||
kernel | ||
kvm | ||
lib | ||
math-emu | ||
mm | ||
oprofile | ||
platforms | ||
sysdev | ||
xmon | ||
Kconfig | ||
Kconfig.debug | ||
Makefile |