df595746fa
When system enter suspend, we can set the DDR IO to high-Z state to save DDR IOs' power consumption, this operation can save many power(from ~26mA@1.5V to ~15mA@1.5V, measured on i.MX6Q SabreSD board, R25) of DDR IOs. To achieve that, we need to copy the suspend code to ocram and run the low level hardware related code(set DDR IOs to high-Z state) in ocram. If there is no ocram space available, then system will still do suspend in external DDR, hence no DDR IOs will be set to high-Z. The OCRAM usage layout is as below, ocram suspend region(4K currently): ======================== high address ====================== . . . ^ ^ ^ imx6_suspend code PM_INFO structure(imx6_cpu_pm_info) ======================== low address ======================= Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
326 lines
7.5 KiB
C
326 lines
7.5 KiB
C
/*
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* Copyright 2011-2013 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/cpu.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/pm_opp.h>
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#include <linux/pci.h>
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#include <linux/phy.h>
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#include <linux/reboot.h>
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#include <linux/regmap.h>
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#include <linux/micrel_phy.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/system_misc.h>
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#include "common.h"
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#include "cpuidle.h"
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#include "hardware.h"
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/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
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static int ksz9021rn_phy_fixup(struct phy_device *phydev)
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{
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if (IS_BUILTIN(CONFIG_PHYLIB)) {
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/* min rx data delay */
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phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
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0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW);
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phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
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/* max rx/tx clock delay, min rx/tx control delay */
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phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
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0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
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phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
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phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
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MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
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}
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return 0;
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}
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static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
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{
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phy_write(dev, 0x0d, device);
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phy_write(dev, 0x0e, reg);
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phy_write(dev, 0x0d, (1 << 14) | device);
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phy_write(dev, 0x0e, val);
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}
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static int ksz9031rn_phy_fixup(struct phy_device *dev)
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{
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/*
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* min rx data delay, max rx/tx clock delay,
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* min rx/tx control delay
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*/
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mmd_write_reg(dev, 2, 4, 0);
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mmd_write_reg(dev, 2, 5, 0);
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mmd_write_reg(dev, 2, 8, 0x003ff);
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return 0;
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}
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/*
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* fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
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* as they are used for slots1-7 PERST#
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*/
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static void ventana_pciesw_early_fixup(struct pci_dev *dev)
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{
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u32 dw;
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if (!of_machine_is_compatible("gw,ventana"))
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return;
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if (dev->devfn != 0)
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return;
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pci_read_config_dword(dev, 0x62c, &dw);
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dw |= 0xaaa8; // GPIO1-7 outputs
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pci_write_config_dword(dev, 0x62c, dw);
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pci_read_config_dword(dev, 0x644, &dw);
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dw |= 0xfe; // GPIO1-7 output high
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pci_write_config_dword(dev, 0x644, dw);
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msleep(100);
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);
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static int ar8031_phy_fixup(struct phy_device *dev)
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{
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u16 val;
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/* To enable AR8031 output a 125MHz clk from CLK_25M */
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phy_write(dev, 0xd, 0x7);
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phy_write(dev, 0xe, 0x8016);
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phy_write(dev, 0xd, 0x4007);
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val = phy_read(dev, 0xe);
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val &= 0xffe3;
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val |= 0x18;
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phy_write(dev, 0xe, val);
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/* introduce tx clock delay */
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phy_write(dev, 0x1d, 0x5);
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val = phy_read(dev, 0x1e);
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val |= 0x0100;
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phy_write(dev, 0x1e, val);
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return 0;
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}
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#define PHY_ID_AR8031 0x004dd074
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static int ar8035_phy_fixup(struct phy_device *dev)
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{
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u16 val;
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/* Ar803x phy SmartEEE feature cause link status generates glitch,
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* which cause ethernet link down/up issue, so disable SmartEEE
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*/
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phy_write(dev, 0xd, 0x3);
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phy_write(dev, 0xe, 0x805d);
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phy_write(dev, 0xd, 0x4003);
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val = phy_read(dev, 0xe);
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phy_write(dev, 0xe, val & ~(1 << 8));
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/*
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* Enable 125MHz clock from CLK_25M on the AR8031. This
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* is fed in to the IMX6 on the ENET_REF_CLK (V22) pad.
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* Also, introduce a tx clock delay.
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*
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* This is the same as is the AR8031 fixup.
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*/
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ar8031_phy_fixup(dev);
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/*check phy power*/
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val = phy_read(dev, 0x0);
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if (val & BMCR_PDOWN)
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phy_write(dev, 0x0, val & ~BMCR_PDOWN);
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return 0;
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}
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#define PHY_ID_AR8035 0x004dd072
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static void __init imx6q_enet_phy_init(void)
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{
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if (IS_BUILTIN(CONFIG_PHYLIB)) {
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phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
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ksz9021rn_phy_fixup);
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phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
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ksz9031rn_phy_fixup);
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phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
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ar8031_phy_fixup);
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phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
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ar8035_phy_fixup);
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}
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}
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static void __init imx6q_1588_init(void)
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{
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struct regmap *gpr;
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gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
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if (!IS_ERR(gpr))
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regmap_update_bits(gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_ENET_CLK_SEL_MASK,
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IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
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else
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pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
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}
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static void __init imx6q_init_machine(void)
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{
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struct device *parent;
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imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
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imx_get_soc_revision());
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mxc_arch_reset_init_dt();
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parent = imx_soc_device_init();
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if (parent == NULL)
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pr_warn("failed to initialize soc device\n");
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imx6q_enet_phy_init();
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of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
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imx_anatop_init();
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cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init();
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imx6q_1588_init();
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}
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#define OCOTP_CFG3 0x440
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#define OCOTP_CFG3_SPEED_SHIFT 16
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#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
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static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
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{
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struct device_node *np;
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void __iomem *base;
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u32 val;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
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if (!np) {
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pr_warn("failed to find ocotp node\n");
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return;
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}
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base = of_iomap(np, 0);
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if (!base) {
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pr_warn("failed to map ocotp\n");
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goto put_node;
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}
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val = readl_relaxed(base + OCOTP_CFG3);
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val >>= OCOTP_CFG3_SPEED_SHIFT;
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if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
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if (dev_pm_opp_disable(cpu_dev, 1200000000))
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pr_warn("failed to disable 1.2 GHz OPP\n");
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put_node:
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of_node_put(np);
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}
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static void __init imx6q_opp_init(void)
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{
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struct device_node *np;
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struct device *cpu_dev = get_cpu_device(0);
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if (!cpu_dev) {
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pr_warn("failed to get cpu0 device\n");
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return;
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}
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np = of_node_get(cpu_dev->of_node);
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if (!np) {
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pr_warn("failed to find cpu0 node\n");
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return;
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}
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if (of_init_opp_table(cpu_dev)) {
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pr_warn("failed to init OPP table\n");
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goto put_node;
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}
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imx6q_opp_check_1p2ghz(cpu_dev);
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put_node:
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of_node_put(np);
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}
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static struct platform_device imx6q_cpufreq_pdev = {
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.name = "imx6q-cpufreq",
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};
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static void __init imx6q_init_late(void)
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{
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/*
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* WAIT mode is broken on TO 1.0 and 1.1, so there is no point
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* to run cpuidle on them.
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*/
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if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1)
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imx6q_cpuidle_init();
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if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
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imx6q_opp_init();
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platform_device_register(&imx6q_cpufreq_pdev);
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}
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}
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static void __init imx6q_map_io(void)
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{
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debug_ll_io_init();
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imx_scu_map_io();
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}
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static void __init imx6q_init_irq(void)
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{
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imx_init_revision_from_anatop();
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imx_init_l2cache();
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imx_src_init();
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imx_gpc_init();
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irqchip_init();
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}
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static const char *imx6q_dt_compat[] __initconst = {
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"fsl,imx6dl",
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"fsl,imx6q",
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NULL,
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};
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DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
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.smp = smp_ops(imx_smp_ops),
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.map_io = imx6q_map_io,
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.init_irq = imx6q_init_irq,
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.init_machine = imx6q_init_machine,
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.init_late = imx6q_init_late,
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.dt_compat = imx6q_dt_compat,
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.restart = mxc_restart,
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MACHINE_END
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