forked from Minki/linux
a1a499a399
Fix following trivial style problems: ERROR: trailing whitespace X 4 WARNING: Use #include <linux/io.h> instead of <asm/io.h> WARNING: braces {} are not necessary for single statement blocks X 3 ERROR: "foo * bar" should be "foo *bar" WARNING: line over 80 characters X 6 ERROR: "foo * bar" should be "foo *bar" ERROR: spaces required around that '=' (ctx:VxO) ERROR: space required before that '-' (ctx:OxV) WARNING: suspect code indent for conditional statements (8, 12) ERROR: spaces required around that '=' (ctx:VxV) ERROR: do not initialise statics to 0 or NULL ERROR: space prohibited after that open parenthesis '(' X 2 ERROR: space prohibited before that close parenthesis ')' X 2 ERROR: trailing statements should be on next line ERROR: return is not a function, parentheses are not required Also use pr_debug and pr_warning where possible. arch/x86/kernel/cpu/mtrr/generic.o: text data bss dec hex filename 5652 77 4224 9953 26e1 generic.o.before 5652 77 4220 9949 26dd generic.o.after The md5 changed: b34d6c045f06daa4ed092b90cc760e8f generic.o.before.asm a490c6251cfd8442fbffecc0e09a573d generic.o.after.asm Because mtrr_state moved from data to bss, changing its offsets - and also because __LINE__ numbers changed. Suggested-by: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Yinghai Lu <yinghai@kernel.org> LKML-Reference: <20090703164225.GA21447@elte.hu> [ Further cleanups to make the code more consistent ] Signed-off-by: Ingo Molnar <mingo@elte.hu>
764 lines
19 KiB
C
764 lines
19 KiB
C
/*
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* This only handles 32bit MTRR on 32bit hosts. This is strictly wrong
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* because MTRRs can span upto 40 bits (36bits on most modern x86)
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*/
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#define DEBUG
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <asm/processor-flags.h>
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#include <asm/cpufeature.h>
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#include <asm/tlbflush.h>
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#include <asm/system.h>
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#include <asm/mtrr.h>
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#include <asm/msr.h>
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#include <asm/pat.h>
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#include "mtrr.h"
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struct fixed_range_block {
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int base_msr; /* start address of an MTRR block */
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int ranges; /* number of MTRRs in this block */
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};
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static struct fixed_range_block fixed_range_blocks[] = {
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{ MSR_MTRRfix64K_00000, 1 }, /* one 64k MTRR */
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{ MSR_MTRRfix16K_80000, 2 }, /* two 16k MTRRs */
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{ MSR_MTRRfix4K_C0000, 8 }, /* eight 4k MTRRs */
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{}
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};
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static unsigned long smp_changes_mask;
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static int mtrr_state_set;
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u64 mtrr_tom2;
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struct mtrr_state_type mtrr_state;
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EXPORT_SYMBOL_GPL(mtrr_state);
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/*
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* BIOS is expected to clear MtrrFixDramModEn bit, see for example
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* "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD
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* Opteron Processors" (26094 Rev. 3.30 February 2006), section
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* "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set
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* to 1 during BIOS initalization of the fixed MTRRs, then cleared to
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* 0 for operation."
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*/
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static inline void k8_check_syscfg_dram_mod_en(void)
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{
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u32 lo, hi;
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if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
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(boot_cpu_data.x86 >= 0x0f)))
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return;
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rdmsr(MSR_K8_SYSCFG, lo, hi);
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if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) {
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printk(KERN_ERR FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]"
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" not cleared by BIOS, clearing this bit\n",
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smp_processor_id());
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lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
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mtrr_wrmsr(MSR_K8_SYSCFG, lo, hi);
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}
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}
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/*
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* Returns the effective MTRR type for the region
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* Error returns:
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* - 0xFE - when the range is "not entirely covered" by _any_ var range MTRR
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* - 0xFF - when MTRR is not enabled
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*/
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u8 mtrr_type_lookup(u64 start, u64 end)
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{
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int i;
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u64 base, mask;
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u8 prev_match, curr_match;
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if (!mtrr_state_set)
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return 0xFF;
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if (!mtrr_state.enabled)
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return 0xFF;
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/* Make end inclusive end, instead of exclusive */
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end--;
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/* Look in fixed ranges. Just return the type as per start */
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if (mtrr_state.have_fixed && (start < 0x100000)) {
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int idx;
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if (start < 0x80000) {
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idx = 0;
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idx += (start >> 16);
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return mtrr_state.fixed_ranges[idx];
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} else if (start < 0xC0000) {
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idx = 1 * 8;
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idx += ((start - 0x80000) >> 14);
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return mtrr_state.fixed_ranges[idx];
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} else if (start < 0x1000000) {
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idx = 3 * 8;
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idx += ((start - 0xC0000) >> 12);
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return mtrr_state.fixed_ranges[idx];
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}
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}
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/*
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* Look in variable ranges
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* Look of multiple ranges matching this address and pick type
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* as per MTRR precedence
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*/
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if (!(mtrr_state.enabled & 2))
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return mtrr_state.def_type;
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prev_match = 0xFF;
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for (i = 0; i < num_var_ranges; ++i) {
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unsigned short start_state, end_state;
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if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11)))
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continue;
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base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) +
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(mtrr_state.var_ranges[i].base_lo & PAGE_MASK);
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mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) +
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(mtrr_state.var_ranges[i].mask_lo & PAGE_MASK);
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start_state = ((start & mask) == (base & mask));
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end_state = ((end & mask) == (base & mask));
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if (start_state != end_state)
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return 0xFE;
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if ((start & mask) != (base & mask))
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continue;
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curr_match = mtrr_state.var_ranges[i].base_lo & 0xff;
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if (prev_match == 0xFF) {
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prev_match = curr_match;
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continue;
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}
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if (prev_match == MTRR_TYPE_UNCACHABLE ||
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curr_match == MTRR_TYPE_UNCACHABLE) {
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return MTRR_TYPE_UNCACHABLE;
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}
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if ((prev_match == MTRR_TYPE_WRBACK &&
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curr_match == MTRR_TYPE_WRTHROUGH) ||
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(prev_match == MTRR_TYPE_WRTHROUGH &&
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curr_match == MTRR_TYPE_WRBACK)) {
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prev_match = MTRR_TYPE_WRTHROUGH;
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curr_match = MTRR_TYPE_WRTHROUGH;
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}
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if (prev_match != curr_match)
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return MTRR_TYPE_UNCACHABLE;
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}
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if (mtrr_tom2) {
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if (start >= (1ULL<<32) && (end < mtrr_tom2))
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return MTRR_TYPE_WRBACK;
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}
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if (prev_match != 0xFF)
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return prev_match;
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return mtrr_state.def_type;
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}
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/* Get the MSR pair relating to a var range */
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static void
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get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
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{
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rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
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rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
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}
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/* Fill the MSR pair relating to a var range */
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void fill_mtrr_var_range(unsigned int index,
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u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi)
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{
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struct mtrr_var_range *vr;
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vr = mtrr_state.var_ranges;
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vr[index].base_lo = base_lo;
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vr[index].base_hi = base_hi;
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vr[index].mask_lo = mask_lo;
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vr[index].mask_hi = mask_hi;
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}
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static void get_fixed_ranges(mtrr_type *frs)
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{
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unsigned int *p = (unsigned int *)frs;
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int i;
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k8_check_syscfg_dram_mod_en();
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rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]);
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for (i = 0; i < 2; i++)
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rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]);
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for (i = 0; i < 8; i++)
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rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]);
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}
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void mtrr_save_fixed_ranges(void *info)
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{
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if (cpu_has_mtrr)
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get_fixed_ranges(mtrr_state.fixed_ranges);
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}
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static unsigned __initdata last_fixed_start;
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static unsigned __initdata last_fixed_end;
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static mtrr_type __initdata last_fixed_type;
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static void __init print_fixed_last(void)
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{
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if (!last_fixed_end)
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return;
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pr_debug(" %05X-%05X %s\n", last_fixed_start,
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last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type));
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last_fixed_end = 0;
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}
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static void __init update_fixed_last(unsigned base, unsigned end,
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mtrr_type type)
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{
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last_fixed_start = base;
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last_fixed_end = end;
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last_fixed_type = type;
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}
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static void __init
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print_fixed(unsigned base, unsigned step, const mtrr_type *types)
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{
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unsigned i;
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for (i = 0; i < 8; ++i, ++types, base += step) {
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if (last_fixed_end == 0) {
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update_fixed_last(base, base + step, *types);
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continue;
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}
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if (last_fixed_end == base && last_fixed_type == *types) {
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last_fixed_end = base + step;
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continue;
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}
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/* new segments: gap or different type */
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print_fixed_last();
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update_fixed_last(base, base + step, *types);
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}
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}
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static void prepare_set(void);
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static void post_set(void);
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static void __init print_mtrr_state(void)
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{
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unsigned int i;
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int high_width;
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pr_debug("MTRR default type: %s\n",
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mtrr_attrib_to_str(mtrr_state.def_type));
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if (mtrr_state.have_fixed) {
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pr_debug("MTRR fixed ranges %sabled:\n",
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mtrr_state.enabled & 1 ? "en" : "dis");
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print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0);
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for (i = 0; i < 2; ++i)
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print_fixed(0x80000 + i * 0x20000, 0x04000,
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mtrr_state.fixed_ranges + (i + 1) * 8);
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for (i = 0; i < 8; ++i)
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print_fixed(0xC0000 + i * 0x08000, 0x01000,
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mtrr_state.fixed_ranges + (i + 3) * 8);
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/* tail */
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print_fixed_last();
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}
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pr_debug("MTRR variable ranges %sabled:\n",
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mtrr_state.enabled & 2 ? "en" : "dis");
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if (size_or_mask & 0xffffffffUL)
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high_width = ffs(size_or_mask & 0xffffffffUL) - 1;
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else
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high_width = ffs(size_or_mask>>32) + 32 - 1;
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high_width = (high_width - (32 - PAGE_SHIFT) + 3) / 4;
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for (i = 0; i < num_var_ranges; ++i) {
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if (mtrr_state.var_ranges[i].mask_lo & (1 << 11))
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pr_debug(" %u base %0*X%05X000 mask %0*X%05X000 %s\n",
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i,
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high_width,
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mtrr_state.var_ranges[i].base_hi,
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mtrr_state.var_ranges[i].base_lo >> 12,
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high_width,
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mtrr_state.var_ranges[i].mask_hi,
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mtrr_state.var_ranges[i].mask_lo >> 12,
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mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff));
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else
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pr_debug(" %u disabled\n", i);
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}
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if (mtrr_tom2)
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pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);
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}
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/* Grab all of the MTRR state for this CPU into *state */
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void __init get_mtrr_state(void)
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{
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struct mtrr_var_range *vrs;
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unsigned long flags;
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unsigned lo, dummy;
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unsigned int i;
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vrs = mtrr_state.var_ranges;
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rdmsr(MSR_MTRRcap, lo, dummy);
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mtrr_state.have_fixed = (lo >> 8) & 1;
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for (i = 0; i < num_var_ranges; i++)
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get_mtrr_var_range(i, &vrs[i]);
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if (mtrr_state.have_fixed)
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get_fixed_ranges(mtrr_state.fixed_ranges);
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rdmsr(MSR_MTRRdefType, lo, dummy);
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mtrr_state.def_type = (lo & 0xff);
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mtrr_state.enabled = (lo & 0xc00) >> 10;
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if (amd_special_default_mtrr()) {
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unsigned low, high;
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/* TOP_MEM2 */
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rdmsr(MSR_K8_TOP_MEM2, low, high);
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mtrr_tom2 = high;
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mtrr_tom2 <<= 32;
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mtrr_tom2 |= low;
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mtrr_tom2 &= 0xffffff800000ULL;
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}
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print_mtrr_state();
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mtrr_state_set = 1;
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/* PAT setup for BP. We need to go through sync steps here */
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local_irq_save(flags);
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prepare_set();
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pat_init();
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post_set();
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local_irq_restore(flags);
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}
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/* Some BIOS's are messed up and don't set all MTRRs the same! */
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void __init mtrr_state_warn(void)
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{
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unsigned long mask = smp_changes_mask;
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if (!mask)
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return;
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if (mask & MTRR_CHANGE_MASK_FIXED)
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pr_warning("mtrr: your CPUs had inconsistent fixed MTRR settings\n");
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if (mask & MTRR_CHANGE_MASK_VARIABLE)
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pr_warning("mtrr: your CPUs had inconsistent variable MTRR settings\n");
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if (mask & MTRR_CHANGE_MASK_DEFTYPE)
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pr_warning("mtrr: your CPUs had inconsistent MTRRdefType settings\n");
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printk(KERN_INFO "mtrr: probably your BIOS does not setup all CPUs.\n");
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printk(KERN_INFO "mtrr: corrected configuration.\n");
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}
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/*
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* Doesn't attempt to pass an error out to MTRR users
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* because it's quite complicated in some cases and probably not
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* worth it because the best error handling is to ignore it.
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*/
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void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b)
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{
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if (wrmsr_safe(msr, a, b) < 0) {
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printk(KERN_ERR
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"MTRR: CPU %u: Writing MSR %x to %x:%x failed\n",
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smp_processor_id(), msr, a, b);
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}
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}
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/**
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* set_fixed_range - checks & updates a fixed-range MTRR if it
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* differs from the value it should have
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* @msr: MSR address of the MTTR which should be checked and updated
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* @changed: pointer which indicates whether the MTRR needed to be changed
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* @msrwords: pointer to the MSR values which the MSR should have
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*/
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static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
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{
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unsigned lo, hi;
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rdmsr(msr, lo, hi);
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if (lo != msrwords[0] || hi != msrwords[1]) {
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mtrr_wrmsr(msr, msrwords[0], msrwords[1]);
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*changed = true;
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}
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}
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|
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/**
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* generic_get_free_region - Get a free MTRR.
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* @base: The starting (base) address of the region.
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* @size: The size (in bytes) of the region.
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* @replace_reg: mtrr index to be replaced; set to invalid value if none.
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*
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* Returns: The index of the region on success, else negative on error.
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*/
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int
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generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
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{
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unsigned long lbase, lsize;
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mtrr_type ltype;
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int i, max;
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max = num_var_ranges;
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if (replace_reg >= 0 && replace_reg < max)
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return replace_reg;
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for (i = 0; i < max; ++i) {
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mtrr_if->get(i, &lbase, &lsize, <ype);
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if (lsize == 0)
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return i;
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}
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return -ENOSPC;
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}
|
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|
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static void generic_get_mtrr(unsigned int reg, unsigned long *base,
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unsigned long *size, mtrr_type *type)
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{
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unsigned int mask_lo, mask_hi, base_lo, base_hi;
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unsigned int tmp, hi;
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int cpu;
|
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/*
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* get_mtrr doesn't need to update mtrr_state, also it could be called
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* from any cpu, so try to print it out directly.
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*/
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cpu = get_cpu();
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|
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rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
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|
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if ((mask_lo & 0x800) == 0) {
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/* Invalid (i.e. free) range */
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*base = 0;
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*size = 0;
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*type = 0;
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goto out_put_cpu;
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}
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rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
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/* Work out the shifted address mask: */
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tmp = mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT;
|
|
mask_lo = size_or_mask | tmp;
|
|
|
|
/* Expand tmp with high bits to all 1s: */
|
|
hi = fls(tmp);
|
|
if (hi > 0) {
|
|
tmp |= ~((1<<(hi - 1)) - 1);
|
|
|
|
if (tmp != mask_lo) {
|
|
WARN_ONCE(1, KERN_INFO "mtrr: your BIOS has set up an incorrect mask, fixing it up.\n");
|
|
mask_lo = tmp;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* This works correctly if size is a power of two, i.e. a
|
|
* contiguous range:
|
|
*/
|
|
*size = -mask_lo;
|
|
*base = base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
|
|
*type = base_lo & 0xff;
|
|
|
|
out_put_cpu:
|
|
put_cpu();
|
|
}
|
|
|
|
/**
|
|
* set_fixed_ranges - checks & updates the fixed-range MTRRs if they
|
|
* differ from the saved set
|
|
* @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges()
|
|
*/
|
|
static int set_fixed_ranges(mtrr_type *frs)
|
|
{
|
|
unsigned long long *saved = (unsigned long long *)frs;
|
|
bool changed = false;
|
|
int block = -1, range;
|
|
|
|
k8_check_syscfg_dram_mod_en();
|
|
|
|
while (fixed_range_blocks[++block].ranges) {
|
|
for (range = 0; range < fixed_range_blocks[block].ranges; range++)
|
|
set_fixed_range(fixed_range_blocks[block].base_msr + range,
|
|
&changed, (unsigned int *)saved++);
|
|
}
|
|
|
|
return changed;
|
|
}
|
|
|
|
/*
|
|
* Set the MSR pair relating to a var range.
|
|
* Returns true if changes are made.
|
|
*/
|
|
static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
|
|
{
|
|
unsigned int lo, hi;
|
|
bool changed = false;
|
|
|
|
rdmsr(MTRRphysBase_MSR(index), lo, hi);
|
|
if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL)
|
|
|| (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
|
|
(hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
|
|
|
|
mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
|
|
changed = true;
|
|
}
|
|
|
|
rdmsr(MTRRphysMask_MSR(index), lo, hi);
|
|
|
|
if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL)
|
|
|| (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
|
|
(hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
|
|
mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
|
|
changed = true;
|
|
}
|
|
return changed;
|
|
}
|
|
|
|
static u32 deftype_lo, deftype_hi;
|
|
|
|
/**
|
|
* set_mtrr_state - Set the MTRR state for this CPU.
|
|
*
|
|
* NOTE: The CPU must already be in a safe state for MTRR changes.
|
|
* RETURNS: 0 if no changes made, else a mask indicating what was changed.
|
|
*/
|
|
static unsigned long set_mtrr_state(void)
|
|
{
|
|
unsigned long change_mask = 0;
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < num_var_ranges; i++) {
|
|
if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i]))
|
|
change_mask |= MTRR_CHANGE_MASK_VARIABLE;
|
|
}
|
|
|
|
if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges))
|
|
change_mask |= MTRR_CHANGE_MASK_FIXED;
|
|
|
|
/*
|
|
* Set_mtrr_restore restores the old value of MTRRdefType,
|
|
* so to set it we fiddle with the saved value:
|
|
*/
|
|
if ((deftype_lo & 0xff) != mtrr_state.def_type
|
|
|| ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) {
|
|
|
|
deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type |
|
|
(mtrr_state.enabled << 10);
|
|
change_mask |= MTRR_CHANGE_MASK_DEFTYPE;
|
|
}
|
|
|
|
return change_mask;
|
|
}
|
|
|
|
|
|
static unsigned long cr4;
|
|
static DEFINE_SPINLOCK(set_atomicity_lock);
|
|
|
|
/*
|
|
* Since we are disabling the cache don't allow any interrupts,
|
|
* they would run extremely slow and would only increase the pain.
|
|
*
|
|
* The caller must ensure that local interrupts are disabled and
|
|
* are reenabled after post_set() has been called.
|
|
*/
|
|
static void prepare_set(void) __acquires(set_atomicity_lock)
|
|
{
|
|
unsigned long cr0;
|
|
|
|
/*
|
|
* Note that this is not ideal
|
|
* since the cache is only flushed/disabled for this CPU while the
|
|
* MTRRs are changed, but changing this requires more invasive
|
|
* changes to the way the kernel boots
|
|
*/
|
|
|
|
spin_lock(&set_atomicity_lock);
|
|
|
|
/* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
|
|
cr0 = read_cr0() | X86_CR0_CD;
|
|
write_cr0(cr0);
|
|
wbinvd();
|
|
|
|
/* Save value of CR4 and clear Page Global Enable (bit 7) */
|
|
if (cpu_has_pge) {
|
|
cr4 = read_cr4();
|
|
write_cr4(cr4 & ~X86_CR4_PGE);
|
|
}
|
|
|
|
/* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
|
|
__flush_tlb();
|
|
|
|
/* Save MTRR state */
|
|
rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
|
|
|
|
/* Disable MTRRs, and set the default type to uncached */
|
|
mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);
|
|
}
|
|
|
|
static void post_set(void) __releases(set_atomicity_lock)
|
|
{
|
|
/* Flush TLBs (no need to flush caches - they are disabled) */
|
|
__flush_tlb();
|
|
|
|
/* Intel (P6) standard MTRRs */
|
|
mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
|
|
|
|
/* Enable caches */
|
|
write_cr0(read_cr0() & 0xbfffffff);
|
|
|
|
/* Restore value of CR4 */
|
|
if (cpu_has_pge)
|
|
write_cr4(cr4);
|
|
spin_unlock(&set_atomicity_lock);
|
|
}
|
|
|
|
static void generic_set_all(void)
|
|
{
|
|
unsigned long mask, count;
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
prepare_set();
|
|
|
|
/* Actually set the state */
|
|
mask = set_mtrr_state();
|
|
|
|
/* also set PAT */
|
|
pat_init();
|
|
|
|
post_set();
|
|
local_irq_restore(flags);
|
|
|
|
/* Use the atomic bitops to update the global mask */
|
|
for (count = 0; count < sizeof mask * 8; ++count) {
|
|
if (mask & 0x01)
|
|
set_bit(count, &smp_changes_mask);
|
|
mask >>= 1;
|
|
}
|
|
|
|
}
|
|
|
|
/**
|
|
* generic_set_mtrr - set variable MTRR register on the local CPU.
|
|
*
|
|
* @reg: The register to set.
|
|
* @base: The base address of the region.
|
|
* @size: The size of the region. If this is 0 the region is disabled.
|
|
* @type: The type of the region.
|
|
*
|
|
* Returns nothing.
|
|
*/
|
|
static void generic_set_mtrr(unsigned int reg, unsigned long base,
|
|
unsigned long size, mtrr_type type)
|
|
{
|
|
unsigned long flags;
|
|
struct mtrr_var_range *vr;
|
|
|
|
vr = &mtrr_state.var_ranges[reg];
|
|
|
|
local_irq_save(flags);
|
|
prepare_set();
|
|
|
|
if (size == 0) {
|
|
/*
|
|
* The invalid bit is kept in the mask, so we simply
|
|
* clear the relevant mask register to disable a range.
|
|
*/
|
|
mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0);
|
|
memset(vr, 0, sizeof(struct mtrr_var_range));
|
|
} else {
|
|
vr->base_lo = base << PAGE_SHIFT | type;
|
|
vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT);
|
|
vr->mask_lo = -size << PAGE_SHIFT | 0x800;
|
|
vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT);
|
|
|
|
mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi);
|
|
mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi);
|
|
}
|
|
|
|
post_set();
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
int generic_validate_add_page(unsigned long base, unsigned long size,
|
|
unsigned int type)
|
|
{
|
|
unsigned long lbase, last;
|
|
|
|
/*
|
|
* For Intel PPro stepping <= 7
|
|
* must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF
|
|
*/
|
|
if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
|
|
boot_cpu_data.x86_model == 1 &&
|
|
boot_cpu_data.x86_mask <= 7) {
|
|
if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
|
|
pr_warning("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
|
|
return -EINVAL;
|
|
}
|
|
if (!(base + size < 0x70000 || base > 0x7003F) &&
|
|
(type == MTRR_TYPE_WRCOMB
|
|
|| type == MTRR_TYPE_WRBACK)) {
|
|
pr_warning("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Check upper bits of base and last are equal and lower bits are 0
|
|
* for base and 1 for last
|
|
*/
|
|
last = base + size - 1;
|
|
for (lbase = base; !(lbase & 1) && (last & 1);
|
|
lbase = lbase >> 1, last = last >> 1)
|
|
;
|
|
if (lbase != last) {
|
|
pr_warning("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size);
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int generic_have_wrcomb(void)
|
|
{
|
|
unsigned long config, dummy;
|
|
rdmsr(MSR_MTRRcap, config, dummy);
|
|
return config & (1 << 10);
|
|
}
|
|
|
|
int positive_have_wrcomb(void)
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* Generic structure...
|
|
*/
|
|
struct mtrr_ops generic_mtrr_ops = {
|
|
.use_intel_if = 1,
|
|
.set_all = generic_set_all,
|
|
.get = generic_get_mtrr,
|
|
.get_free_region = generic_get_free_region,
|
|
.set = generic_set_mtrr,
|
|
.validate_add_page = generic_validate_add_page,
|
|
.have_wrcomb = generic_have_wrcomb,
|
|
};
|