forked from Minki/linux
de5b867741
Cleanup by making local functions static. The code to load config file is unreachable in net-next, probably came from some out of tree driver. Signed-off-by: Stephen Hemminger <stephen@networkplumber.org> Signed-off-by: David S. Miller <davem@davemloft.net>
1011 lines
34 KiB
C
1011 lines
34 KiB
C
/*
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* This file is part of the Chelsio T4 Ethernet driver for Linux.
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*
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* Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __CXGB4_H__
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#define __CXGB4_H__
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#include "t4_hw.h"
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#include <linux/bitops.h>
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#include <linux/cache.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/netdevice.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <linux/timer.h>
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#include <linux/vmalloc.h>
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#include <asm/io.h>
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#include "cxgb4_uld.h"
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#define T4FW_VERSION_MAJOR 0x01
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#define T4FW_VERSION_MINOR 0x06
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#define T4FW_VERSION_MICRO 0x18
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#define T4FW_VERSION_BUILD 0x00
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#define T5FW_VERSION_MAJOR 0x01
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#define T5FW_VERSION_MINOR 0x08
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#define T5FW_VERSION_MICRO 0x1C
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#define T5FW_VERSION_BUILD 0x00
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#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
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enum {
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MAX_NPORTS = 4, /* max # of ports */
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SERNUM_LEN = 24, /* Serial # length */
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EC_LEN = 16, /* E/C length */
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ID_LEN = 16, /* ID length */
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};
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enum {
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MEM_EDC0,
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MEM_EDC1,
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MEM_MC,
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MEM_MC0 = MEM_MC,
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MEM_MC1
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};
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enum {
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MEMWIN0_APERTURE = 2048,
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MEMWIN0_BASE = 0x1b800,
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MEMWIN1_APERTURE = 32768,
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MEMWIN1_BASE = 0x28000,
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MEMWIN1_BASE_T5 = 0x52000,
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MEMWIN2_APERTURE = 65536,
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MEMWIN2_BASE = 0x30000,
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MEMWIN2_BASE_T5 = 0x54000,
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};
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enum dev_master {
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MASTER_CANT,
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MASTER_MAY,
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MASTER_MUST
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};
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enum dev_state {
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DEV_STATE_UNINIT,
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DEV_STATE_INIT,
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DEV_STATE_ERR
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};
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enum {
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PAUSE_RX = 1 << 0,
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PAUSE_TX = 1 << 1,
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PAUSE_AUTONEG = 1 << 2
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};
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struct port_stats {
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u64 tx_octets; /* total # of octets in good frames */
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u64 tx_frames; /* all good frames */
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u64 tx_bcast_frames; /* all broadcast frames */
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u64 tx_mcast_frames; /* all multicast frames */
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u64 tx_ucast_frames; /* all unicast frames */
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u64 tx_error_frames; /* all error frames */
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u64 tx_frames_64; /* # of Tx frames in a particular range */
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u64 tx_frames_65_127;
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u64 tx_frames_128_255;
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u64 tx_frames_256_511;
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u64 tx_frames_512_1023;
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u64 tx_frames_1024_1518;
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u64 tx_frames_1519_max;
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u64 tx_drop; /* # of dropped Tx frames */
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u64 tx_pause; /* # of transmitted pause frames */
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u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
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u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
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u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
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u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
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u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
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u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
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u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
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u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
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u64 rx_octets; /* total # of octets in good frames */
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u64 rx_frames; /* all good frames */
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u64 rx_bcast_frames; /* all broadcast frames */
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u64 rx_mcast_frames; /* all multicast frames */
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u64 rx_ucast_frames; /* all unicast frames */
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u64 rx_too_long; /* # of frames exceeding MTU */
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u64 rx_jabber; /* # of jabber frames */
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u64 rx_fcs_err; /* # of received frames with bad FCS */
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u64 rx_len_err; /* # of received frames with length error */
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u64 rx_symbol_err; /* symbol errors */
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u64 rx_runt; /* # of short frames */
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u64 rx_frames_64; /* # of Rx frames in a particular range */
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u64 rx_frames_65_127;
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u64 rx_frames_128_255;
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u64 rx_frames_256_511;
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u64 rx_frames_512_1023;
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u64 rx_frames_1024_1518;
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u64 rx_frames_1519_max;
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u64 rx_pause; /* # of received pause frames */
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u64 rx_ppp0; /* # of received PPP prio 0 frames */
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u64 rx_ppp1; /* # of received PPP prio 1 frames */
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u64 rx_ppp2; /* # of received PPP prio 2 frames */
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u64 rx_ppp3; /* # of received PPP prio 3 frames */
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u64 rx_ppp4; /* # of received PPP prio 4 frames */
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u64 rx_ppp5; /* # of received PPP prio 5 frames */
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u64 rx_ppp6; /* # of received PPP prio 6 frames */
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u64 rx_ppp7; /* # of received PPP prio 7 frames */
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u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
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u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
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u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
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u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
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u64 rx_trunc0; /* buffer-group 0 truncated packets */
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u64 rx_trunc1; /* buffer-group 1 truncated packets */
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u64 rx_trunc2; /* buffer-group 2 truncated packets */
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u64 rx_trunc3; /* buffer-group 3 truncated packets */
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};
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struct lb_port_stats {
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u64 octets;
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u64 frames;
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u64 bcast_frames;
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u64 mcast_frames;
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u64 ucast_frames;
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u64 error_frames;
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u64 frames_64;
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u64 frames_65_127;
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u64 frames_128_255;
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u64 frames_256_511;
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u64 frames_512_1023;
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u64 frames_1024_1518;
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u64 frames_1519_max;
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u64 drop;
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u64 ovflow0;
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u64 ovflow1;
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u64 ovflow2;
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u64 ovflow3;
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u64 trunc0;
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u64 trunc1;
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u64 trunc2;
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u64 trunc3;
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};
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struct tp_tcp_stats {
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u32 tcpOutRsts;
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u64 tcpInSegs;
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u64 tcpOutSegs;
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u64 tcpRetransSegs;
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};
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struct tp_err_stats {
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u32 macInErrs[4];
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u32 hdrInErrs[4];
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u32 tcpInErrs[4];
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u32 tnlCongDrops[4];
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u32 ofldChanDrops[4];
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u32 tnlTxDrops[4];
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u32 ofldVlanDrops[4];
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u32 tcp6InErrs[4];
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u32 ofldNoNeigh;
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u32 ofldCongDefer;
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};
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struct tp_params {
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unsigned int ntxchan; /* # of Tx channels */
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unsigned int tre; /* log2 of core clocks per TP tick */
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unsigned short tx_modq_map; /* TX modulation scheduler queue to */
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/* channel map */
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uint32_t dack_re; /* DACK timer resolution */
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unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
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};
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struct vpd_params {
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unsigned int cclk;
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u8 ec[EC_LEN + 1];
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u8 sn[SERNUM_LEN + 1];
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u8 id[ID_LEN + 1];
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};
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struct pci_params {
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unsigned char speed;
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unsigned char width;
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};
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#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
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#define CHELSIO_CHIP_FPGA 0x100
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#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
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#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
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#define CHELSIO_T4 0x4
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#define CHELSIO_T5 0x5
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enum chip_type {
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T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
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T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
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T4_FIRST_REV = T4_A1,
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T4_LAST_REV = T4_A2,
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T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
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T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
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T5_FIRST_REV = T5_A0,
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T5_LAST_REV = T5_A1,
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};
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struct adapter_params {
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struct tp_params tp;
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struct vpd_params vpd;
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struct pci_params pci;
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unsigned int sf_size; /* serial flash size in bytes */
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unsigned int sf_nsec; /* # of flash sectors */
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unsigned int sf_fw_start; /* start of FW image in flash */
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unsigned int fw_vers;
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unsigned int tp_vers;
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u8 api_vers[7];
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unsigned short mtus[NMTUS];
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unsigned short a_wnd[NCCTRL_WIN];
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unsigned short b_wnd[NCCTRL_WIN];
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unsigned char nports; /* # of ethernet ports */
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unsigned char portvec;
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enum chip_type chip; /* chip code */
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unsigned char offload;
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unsigned char bypass;
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unsigned int ofldq_wr_cred;
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};
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#include "t4fw_api.h"
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#define FW_VERSION(chip) ( \
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FW_HDR_FW_VER_MAJOR_GET(chip##FW_VERSION_MAJOR) | \
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FW_HDR_FW_VER_MINOR_GET(chip##FW_VERSION_MINOR) | \
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FW_HDR_FW_VER_MICRO_GET(chip##FW_VERSION_MICRO) | \
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FW_HDR_FW_VER_BUILD_GET(chip##FW_VERSION_BUILD))
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#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
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struct fw_info {
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u8 chip;
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char *fs_name;
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char *fw_mod_name;
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struct fw_hdr fw_hdr;
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};
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struct trace_params {
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u32 data[TRACE_LEN / 4];
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u32 mask[TRACE_LEN / 4];
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unsigned short snap_len;
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unsigned short min_len;
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unsigned char skip_ofst;
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unsigned char skip_len;
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unsigned char invert;
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unsigned char port;
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};
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struct link_config {
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unsigned short supported; /* link capabilities */
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unsigned short advertising; /* advertised capabilities */
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unsigned short requested_speed; /* speed user has requested */
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unsigned short speed; /* actual link speed */
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unsigned char requested_fc; /* flow control user has requested */
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unsigned char fc; /* actual link flow control */
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unsigned char autoneg; /* autonegotiating? */
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unsigned char link_ok; /* link up? */
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};
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#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
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enum {
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MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
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MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
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MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
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MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
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};
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enum {
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MAX_EGRQ = 128, /* max # of egress queues, including FLs */
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MAX_INGQ = 64 /* max # of interrupt-capable ingress queues */
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};
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struct adapter;
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struct sge_rspq;
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struct port_info {
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struct adapter *adapter;
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u16 viid;
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s16 xact_addr_filt; /* index of exact MAC address filter */
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u16 rss_size; /* size of VI's RSS table slice */
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s8 mdio_addr;
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u8 port_type;
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u8 mod_type;
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u8 port_id;
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u8 tx_chan;
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u8 lport; /* associated offload logical port */
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u8 nqsets; /* # of qsets */
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u8 first_qset; /* index of first qset */
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u8 rss_mode;
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struct link_config link_cfg;
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u16 *rss;
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};
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struct dentry;
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struct work_struct;
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enum { /* adapter flags */
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FULL_INIT_DONE = (1 << 0),
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USING_MSI = (1 << 1),
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USING_MSIX = (1 << 2),
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FW_OK = (1 << 4),
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RSS_TNLALLLOOKUP = (1 << 5),
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USING_SOFT_PARAMS = (1 << 6),
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MASTER_PF = (1 << 7),
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FW_OFLD_CONN = (1 << 9),
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};
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struct rx_sw_desc;
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struct sge_fl { /* SGE free-buffer queue state */
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unsigned int avail; /* # of available Rx buffers */
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unsigned int pend_cred; /* new buffers since last FL DB ring */
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unsigned int cidx; /* consumer index */
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unsigned int pidx; /* producer index */
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unsigned long alloc_failed; /* # of times buffer allocation failed */
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unsigned long large_alloc_failed;
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unsigned long starving;
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/* RO fields */
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unsigned int cntxt_id; /* SGE context id for the free list */
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unsigned int size; /* capacity of free list */
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struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
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__be64 *desc; /* address of HW Rx descriptor ring */
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dma_addr_t addr; /* bus address of HW ring start */
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};
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/* A packet gather list */
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struct pkt_gl {
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struct page_frag frags[MAX_SKB_FRAGS];
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void *va; /* virtual address of first byte */
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unsigned int nfrags; /* # of fragments */
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unsigned int tot_len; /* total length of fragments */
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};
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typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
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const struct pkt_gl *gl);
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struct sge_rspq { /* state for an SGE response queue */
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struct napi_struct napi;
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const __be64 *cur_desc; /* current descriptor in queue */
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unsigned int cidx; /* consumer index */
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u8 gen; /* current generation bit */
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u8 intr_params; /* interrupt holdoff parameters */
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u8 next_intr_params; /* holdoff params for next interrupt */
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u8 pktcnt_idx; /* interrupt packet threshold */
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u8 uld; /* ULD handling this queue */
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u8 idx; /* queue index within its group */
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int offset; /* offset into current Rx buffer */
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u16 cntxt_id; /* SGE context id for the response q */
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u16 abs_id; /* absolute SGE id for the response q */
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__be64 *desc; /* address of HW response ring */
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dma_addr_t phys_addr; /* physical address of the ring */
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unsigned int iqe_len; /* entry size */
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unsigned int size; /* capacity of response queue */
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struct adapter *adap;
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struct net_device *netdev; /* associated net device */
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rspq_handler_t handler;
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};
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struct sge_eth_stats { /* Ethernet queue statistics */
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unsigned long pkts; /* # of ethernet packets */
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unsigned long lro_pkts; /* # of LRO super packets */
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unsigned long lro_merged; /* # of wire packets merged by LRO */
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unsigned long rx_cso; /* # of Rx checksum offloads */
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unsigned long vlan_ex; /* # of Rx VLAN extractions */
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unsigned long rx_drops; /* # of packets dropped due to no mem */
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};
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struct sge_eth_rxq { /* SW Ethernet Rx queue */
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struct sge_rspq rspq;
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struct sge_fl fl;
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struct sge_eth_stats stats;
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} ____cacheline_aligned_in_smp;
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struct sge_ofld_stats { /* offload queue statistics */
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unsigned long pkts; /* # of packets */
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unsigned long imm; /* # of immediate-data packets */
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unsigned long an; /* # of asynchronous notifications */
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unsigned long nomem; /* # of responses deferred due to no mem */
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};
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struct sge_ofld_rxq { /* SW offload Rx queue */
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struct sge_rspq rspq;
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struct sge_fl fl;
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struct sge_ofld_stats stats;
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} ____cacheline_aligned_in_smp;
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struct tx_desc {
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__be64 flit[8];
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};
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struct tx_sw_desc;
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struct sge_txq {
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unsigned int in_use; /* # of in-use Tx descriptors */
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unsigned int size; /* # of descriptors */
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unsigned int cidx; /* SW consumer index */
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unsigned int pidx; /* producer index */
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unsigned long stops; /* # of times q has been stopped */
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unsigned long restarts; /* # of queue restarts */
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unsigned int cntxt_id; /* SGE context id for the Tx q */
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struct tx_desc *desc; /* address of HW Tx descriptor ring */
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struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
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struct sge_qstat *stat; /* queue status entry */
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dma_addr_t phys_addr; /* physical address of the ring */
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spinlock_t db_lock;
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int db_disabled;
|
|
unsigned short db_pidx;
|
|
u64 udb;
|
|
};
|
|
|
|
struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
|
|
struct sge_txq q;
|
|
struct netdev_queue *txq; /* associated netdev TX queue */
|
|
unsigned long tso; /* # of TSO requests */
|
|
unsigned long tx_cso; /* # of Tx checksum offloads */
|
|
unsigned long vlan_ins; /* # of Tx VLAN insertions */
|
|
unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
|
|
} ____cacheline_aligned_in_smp;
|
|
|
|
struct sge_ofld_txq { /* state for an SGE offload Tx queue */
|
|
struct sge_txq q;
|
|
struct adapter *adap;
|
|
struct sk_buff_head sendq; /* list of backpressured packets */
|
|
struct tasklet_struct qresume_tsk; /* restarts the queue */
|
|
u8 full; /* the Tx ring is full */
|
|
unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
|
|
} ____cacheline_aligned_in_smp;
|
|
|
|
struct sge_ctrl_txq { /* state for an SGE control Tx queue */
|
|
struct sge_txq q;
|
|
struct adapter *adap;
|
|
struct sk_buff_head sendq; /* list of backpressured packets */
|
|
struct tasklet_struct qresume_tsk; /* restarts the queue */
|
|
u8 full; /* the Tx ring is full */
|
|
} ____cacheline_aligned_in_smp;
|
|
|
|
struct sge {
|
|
struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
|
|
struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
|
|
struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
|
|
|
|
struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
|
|
struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
|
|
struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
|
|
struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
|
|
|
|
struct sge_rspq intrq ____cacheline_aligned_in_smp;
|
|
spinlock_t intrq_lock;
|
|
|
|
u16 max_ethqsets; /* # of available Ethernet queue sets */
|
|
u16 ethqsets; /* # of active Ethernet queue sets */
|
|
u16 ethtxq_rover; /* Tx queue to clean up next */
|
|
u16 ofldqsets; /* # of active offload queue sets */
|
|
u16 rdmaqs; /* # of available RDMA Rx queues */
|
|
u16 ofld_rxq[MAX_OFLD_QSETS];
|
|
u16 rdma_rxq[NCHAN];
|
|
u16 timer_val[SGE_NTIMERS];
|
|
u8 counter_val[SGE_NCOUNTERS];
|
|
u32 fl_pg_order; /* large page allocation size */
|
|
u32 stat_len; /* length of status page at ring end */
|
|
u32 pktshift; /* padding between CPL & packet data */
|
|
u32 fl_align; /* response queue message alignment */
|
|
u32 fl_starve_thres; /* Free List starvation threshold */
|
|
unsigned int starve_thres;
|
|
u8 idma_state[2];
|
|
unsigned int egr_start;
|
|
unsigned int ingr_start;
|
|
void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */
|
|
struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */
|
|
DECLARE_BITMAP(starving_fl, MAX_EGRQ);
|
|
DECLARE_BITMAP(txq_maperr, MAX_EGRQ);
|
|
struct timer_list rx_timer; /* refills starving FLs */
|
|
struct timer_list tx_timer; /* checks Tx queues */
|
|
};
|
|
|
|
#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
|
|
#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
|
|
#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
|
|
|
|
struct l2t_data;
|
|
|
|
#ifdef CONFIG_PCI_IOV
|
|
|
|
/* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
|
|
* Configuration initialization for T5 only has SR-IOV functionality enabled
|
|
* on PF0-3 in order to simplify everything.
|
|
*/
|
|
#define NUM_OF_PF_WITH_SRIOV 4
|
|
|
|
#endif
|
|
|
|
struct adapter {
|
|
void __iomem *regs;
|
|
void __iomem *bar2;
|
|
struct pci_dev *pdev;
|
|
struct device *pdev_dev;
|
|
unsigned int mbox;
|
|
unsigned int fn;
|
|
unsigned int flags;
|
|
enum chip_type chip;
|
|
|
|
int msg_enable;
|
|
|
|
struct adapter_params params;
|
|
struct cxgb4_virt_res vres;
|
|
unsigned int swintr;
|
|
|
|
unsigned int wol;
|
|
|
|
struct {
|
|
unsigned short vec;
|
|
char desc[IFNAMSIZ + 10];
|
|
} msix_info[MAX_INGQ + 1];
|
|
|
|
struct sge sge;
|
|
|
|
struct net_device *port[MAX_NPORTS];
|
|
u8 chan_map[NCHAN]; /* channel -> port map */
|
|
|
|
u32 filter_mode;
|
|
unsigned int l2t_start;
|
|
unsigned int l2t_end;
|
|
struct l2t_data *l2t;
|
|
void *uld_handle[CXGB4_ULD_MAX];
|
|
struct list_head list_node;
|
|
struct list_head rcu_node;
|
|
|
|
struct tid_info tids;
|
|
void **tid_release_head;
|
|
spinlock_t tid_release_lock;
|
|
struct work_struct tid_release_task;
|
|
struct work_struct db_full_task;
|
|
struct work_struct db_drop_task;
|
|
bool tid_release_task_busy;
|
|
|
|
struct dentry *debugfs_root;
|
|
|
|
spinlock_t stats_lock;
|
|
};
|
|
|
|
/* Defined bit width of user definable filter tuples
|
|
*/
|
|
#define ETHTYPE_BITWIDTH 16
|
|
#define FRAG_BITWIDTH 1
|
|
#define MACIDX_BITWIDTH 9
|
|
#define FCOE_BITWIDTH 1
|
|
#define IPORT_BITWIDTH 3
|
|
#define MATCHTYPE_BITWIDTH 3
|
|
#define PROTO_BITWIDTH 8
|
|
#define TOS_BITWIDTH 8
|
|
#define PF_BITWIDTH 8
|
|
#define VF_BITWIDTH 8
|
|
#define IVLAN_BITWIDTH 16
|
|
#define OVLAN_BITWIDTH 16
|
|
|
|
/* Filter matching rules. These consist of a set of ingress packet field
|
|
* (value, mask) tuples. The associated ingress packet field matches the
|
|
* tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
|
|
* rule can be constructed by specifying a tuple of (0, 0).) A filter rule
|
|
* matches an ingress packet when all of the individual individual field
|
|
* matching rules are true.
|
|
*
|
|
* Partial field masks are always valid, however, while it may be easy to
|
|
* understand their meanings for some fields (e.g. IP address to match a
|
|
* subnet), for others making sensible partial masks is less intuitive (e.g.
|
|
* MPS match type) ...
|
|
*
|
|
* Most of the following data structures are modeled on T4 capabilities.
|
|
* Drivers for earlier chips use the subsets which make sense for those chips.
|
|
* We really need to come up with a hardware-independent mechanism to
|
|
* represent hardware filter capabilities ...
|
|
*/
|
|
struct ch_filter_tuple {
|
|
/* Compressed header matching field rules. The TP_VLAN_PRI_MAP
|
|
* register selects which of these fields will participate in the
|
|
* filter match rules -- up to a maximum of 36 bits. Because
|
|
* TP_VLAN_PRI_MAP is a global register, all filters must use the same
|
|
* set of fields.
|
|
*/
|
|
uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
|
|
uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
|
|
uint32_t ivlan_vld:1; /* inner VLAN valid */
|
|
uint32_t ovlan_vld:1; /* outer VLAN valid */
|
|
uint32_t pfvf_vld:1; /* PF/VF valid */
|
|
uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
|
|
uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
|
|
uint32_t iport:IPORT_BITWIDTH; /* ingress port */
|
|
uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
|
|
uint32_t proto:PROTO_BITWIDTH; /* protocol type */
|
|
uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
|
|
uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
|
|
uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
|
|
uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
|
|
uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
|
|
|
|
/* Uncompressed header matching field rules. These are always
|
|
* available for field rules.
|
|
*/
|
|
uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
|
|
uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
|
|
uint16_t lport; /* local port */
|
|
uint16_t fport; /* foreign port */
|
|
};
|
|
|
|
/* A filter ioctl command.
|
|
*/
|
|
struct ch_filter_specification {
|
|
/* Administrative fields for filter.
|
|
*/
|
|
uint32_t hitcnts:1; /* count filter hits in TCB */
|
|
uint32_t prio:1; /* filter has priority over active/server */
|
|
|
|
/* Fundamental filter typing. This is the one element of filter
|
|
* matching that doesn't exist as a (value, mask) tuple.
|
|
*/
|
|
uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
|
|
|
|
/* Packet dispatch information. Ingress packets which match the
|
|
* filter rules will be dropped, passed to the host or switched back
|
|
* out as egress packets.
|
|
*/
|
|
uint32_t action:2; /* drop, pass, switch */
|
|
|
|
uint32_t rpttid:1; /* report TID in RSS hash field */
|
|
|
|
uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
|
|
uint32_t iq:10; /* ingress queue */
|
|
|
|
uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
|
|
uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
|
|
/* 1 => TCB contains IQ ID */
|
|
|
|
/* Switch proxy/rewrite fields. An ingress packet which matches a
|
|
* filter with "switch" set will be looped back out as an egress
|
|
* packet -- potentially with some Ethernet header rewriting.
|
|
*/
|
|
uint32_t eport:2; /* egress port to switch packet out */
|
|
uint32_t newdmac:1; /* rewrite destination MAC address */
|
|
uint32_t newsmac:1; /* rewrite source MAC address */
|
|
uint32_t newvlan:2; /* rewrite VLAN Tag */
|
|
uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
|
|
uint8_t smac[ETH_ALEN]; /* new source MAC address */
|
|
uint16_t vlan; /* VLAN Tag to insert */
|
|
|
|
/* Filter rule value/mask pairs.
|
|
*/
|
|
struct ch_filter_tuple val;
|
|
struct ch_filter_tuple mask;
|
|
};
|
|
|
|
enum {
|
|
FILTER_PASS = 0, /* default */
|
|
FILTER_DROP,
|
|
FILTER_SWITCH
|
|
};
|
|
|
|
enum {
|
|
VLAN_NOCHANGE = 0, /* default */
|
|
VLAN_REMOVE,
|
|
VLAN_INSERT,
|
|
VLAN_REWRITE
|
|
};
|
|
|
|
static inline int is_t5(enum chip_type chip)
|
|
{
|
|
return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
|
|
}
|
|
|
|
static inline int is_t4(enum chip_type chip)
|
|
{
|
|
return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
|
|
}
|
|
|
|
static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
|
|
{
|
|
return readl(adap->regs + reg_addr);
|
|
}
|
|
|
|
static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
|
|
{
|
|
writel(val, adap->regs + reg_addr);
|
|
}
|
|
|
|
#ifndef readq
|
|
static inline u64 readq(const volatile void __iomem *addr)
|
|
{
|
|
return readl(addr) + ((u64)readl(addr + 4) << 32);
|
|
}
|
|
|
|
static inline void writeq(u64 val, volatile void __iomem *addr)
|
|
{
|
|
writel(val, addr);
|
|
writel(val >> 32, addr + 4);
|
|
}
|
|
#endif
|
|
|
|
static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
|
|
{
|
|
return readq(adap->regs + reg_addr);
|
|
}
|
|
|
|
static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
|
|
{
|
|
writeq(val, adap->regs + reg_addr);
|
|
}
|
|
|
|
/**
|
|
* netdev2pinfo - return the port_info structure associated with a net_device
|
|
* @dev: the netdev
|
|
*
|
|
* Return the struct port_info associated with a net_device
|
|
*/
|
|
static inline struct port_info *netdev2pinfo(const struct net_device *dev)
|
|
{
|
|
return netdev_priv(dev);
|
|
}
|
|
|
|
/**
|
|
* adap2pinfo - return the port_info of a port
|
|
* @adap: the adapter
|
|
* @idx: the port index
|
|
*
|
|
* Return the port_info structure for the port of the given index.
|
|
*/
|
|
static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
|
|
{
|
|
return netdev_priv(adap->port[idx]);
|
|
}
|
|
|
|
/**
|
|
* netdev2adap - return the adapter structure associated with a net_device
|
|
* @dev: the netdev
|
|
*
|
|
* Return the struct adapter associated with a net_device
|
|
*/
|
|
static inline struct adapter *netdev2adap(const struct net_device *dev)
|
|
{
|
|
return netdev2pinfo(dev)->adapter;
|
|
}
|
|
|
|
void t4_os_portmod_changed(const struct adapter *adap, int port_id);
|
|
void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
|
|
|
|
void *t4_alloc_mem(size_t size);
|
|
|
|
void t4_free_sge_resources(struct adapter *adap);
|
|
irq_handler_t t4_intr_handler(struct adapter *adap);
|
|
netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
|
|
int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
|
|
const struct pkt_gl *gl);
|
|
int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
|
|
int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
|
|
int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
|
|
struct net_device *dev, int intr_idx,
|
|
struct sge_fl *fl, rspq_handler_t hnd);
|
|
int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
|
|
struct net_device *dev, struct netdev_queue *netdevq,
|
|
unsigned int iqid);
|
|
int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
|
|
struct net_device *dev, unsigned int iqid,
|
|
unsigned int cmplqid);
|
|
int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
|
|
struct net_device *dev, unsigned int iqid);
|
|
irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
|
|
int t4_sge_init(struct adapter *adap);
|
|
void t4_sge_start(struct adapter *adap);
|
|
void t4_sge_stop(struct adapter *adap);
|
|
extern int dbfifo_int_thresh;
|
|
|
|
#define for_each_port(adapter, iter) \
|
|
for (iter = 0; iter < (adapter)->params.nports; ++iter)
|
|
|
|
static inline int is_bypass(struct adapter *adap)
|
|
{
|
|
return adap->params.bypass;
|
|
}
|
|
|
|
static inline int is_bypass_device(int device)
|
|
{
|
|
/* this should be set based upon device capabilities */
|
|
switch (device) {
|
|
case 0x440b:
|
|
case 0x440c:
|
|
return 1;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
|
|
{
|
|
return adap->params.vpd.cclk / 1000;
|
|
}
|
|
|
|
static inline unsigned int us_to_core_ticks(const struct adapter *adap,
|
|
unsigned int us)
|
|
{
|
|
return (us * adap->params.vpd.cclk) / 1000;
|
|
}
|
|
|
|
static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
|
|
unsigned int ticks)
|
|
{
|
|
/* add Core Clock / 2 to round ticks to nearest uS */
|
|
return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
|
|
adapter->params.vpd.cclk);
|
|
}
|
|
|
|
void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
|
|
u32 val);
|
|
|
|
int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
|
|
void *rpl, bool sleep_ok);
|
|
|
|
static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
|
|
int size, void *rpl)
|
|
{
|
|
return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
|
|
}
|
|
|
|
static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
|
|
int size, void *rpl)
|
|
{
|
|
return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
|
|
}
|
|
|
|
void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
|
|
unsigned int data_reg, const u32 *vals,
|
|
unsigned int nregs, unsigned int start_idx);
|
|
void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
|
|
unsigned int data_reg, u32 *vals, unsigned int nregs,
|
|
unsigned int start_idx);
|
|
|
|
struct fw_filter_wr;
|
|
|
|
void t4_intr_enable(struct adapter *adapter);
|
|
void t4_intr_disable(struct adapter *adapter);
|
|
int t4_slow_intr_handler(struct adapter *adapter);
|
|
|
|
int t4_wait_dev_ready(struct adapter *adap);
|
|
int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
|
|
struct link_config *lc);
|
|
int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
|
|
int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
|
|
__be32 *buf);
|
|
int t4_seeprom_wp(struct adapter *adapter, bool enable);
|
|
int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
|
|
int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
|
|
unsigned int t4_flash_cfg_addr(struct adapter *adapter);
|
|
int t4_get_fw_version(struct adapter *adapter, u32 *vers);
|
|
int t4_get_tp_version(struct adapter *adapter, u32 *vers);
|
|
int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
|
|
const u8 *fw_data, unsigned int fw_size,
|
|
struct fw_hdr *card_fw, enum dev_state state, int *reset);
|
|
int t4_prep_adapter(struct adapter *adapter);
|
|
int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
|
|
void t4_fatal_err(struct adapter *adapter);
|
|
int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
|
|
int start, int n, const u16 *rspq, unsigned int nrspq);
|
|
int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
|
|
unsigned int flags);
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int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
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u64 *parity);
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int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
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u64 *parity);
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void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
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void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
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void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
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unsigned int mask, unsigned int val);
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void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
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struct tp_tcp_stats *v6);
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void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
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const unsigned short *alpha, const unsigned short *beta);
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void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
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void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
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const u8 *addr);
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int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
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u64 mask0, u64 mask1, unsigned int crc, bool enable);
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int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
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enum dev_master master, enum dev_state *state);
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int t4_fw_bye(struct adapter *adap, unsigned int mbox);
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int t4_early_init(struct adapter *adap, unsigned int mbox);
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int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
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int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
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unsigned int cache_line_size);
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int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
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int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
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unsigned int vf, unsigned int nparams, const u32 *params,
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u32 *val);
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int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
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unsigned int vf, unsigned int nparams, const u32 *params,
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const u32 *val);
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int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
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unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
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unsigned int rxqi, unsigned int rxq, unsigned int tc,
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unsigned int vi, unsigned int cmask, unsigned int pmask,
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unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
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int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
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unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
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unsigned int *rss_size);
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int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
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int mtu, int promisc, int all_multi, int bcast, int vlanex,
|
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bool sleep_ok);
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int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
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unsigned int viid, bool free, unsigned int naddr,
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const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
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int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
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int idx, const u8 *addr, bool persist, bool add_smt);
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int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
|
bool ucast, u64 vec, bool sleep_ok);
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int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
|
bool rx_en, bool tx_en);
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int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
|
unsigned int nblinks);
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int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
|
|
unsigned int mmd, unsigned int reg, u16 *valp);
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int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
|
|
unsigned int mmd, unsigned int reg, u16 val);
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int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
|
unsigned int vf, unsigned int iqtype, unsigned int iqid,
|
|
unsigned int fl0id, unsigned int fl1id);
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|
int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
|
unsigned int vf, unsigned int eqid);
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|
int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
|
unsigned int vf, unsigned int eqid);
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|
int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
|
unsigned int vf, unsigned int eqid);
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int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
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|
void t4_db_full(struct adapter *adapter);
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|
void t4_db_dropped(struct adapter *adapter);
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int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len);
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int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
|
|
u32 addr, u32 val);
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#endif /* __CXGB4_H__ */
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