forked from Minki/linux
f6026df1a4
A recent patch added a function prototype for htab_remove_mapping in c code. Fix it. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
594 lines
20 KiB
C
594 lines
20 KiB
C
#ifndef _ASM_POWERPC_MMU_HASH64_H_
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#define _ASM_POWERPC_MMU_HASH64_H_
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/*
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* PowerPC64 memory management structures
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*
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* Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
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* PPC64 rework.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/asm-compat.h>
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#include <asm/page.h>
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/*
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* This is necessary to get the definition of PGTABLE_RANGE which we
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* need for various slices related matters. Note that this isn't the
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* complete pgtable.h but only a portion of it.
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*/
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#include <asm/pgtable-ppc64.h>
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#include <asm/bug.h>
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#include <asm/processor.h>
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/*
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* SLB
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*/
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#define SLB_NUM_BOLTED 3
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#define SLB_CACHE_ENTRIES 8
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#define SLB_MIN_SIZE 32
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/* Bits in the SLB ESID word */
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#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
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/* Bits in the SLB VSID word */
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#define SLB_VSID_SHIFT 12
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#define SLB_VSID_SHIFT_1T 24
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#define SLB_VSID_SSIZE_SHIFT 62
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#define SLB_VSID_B ASM_CONST(0xc000000000000000)
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#define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
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#define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
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#define SLB_VSID_KS ASM_CONST(0x0000000000000800)
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#define SLB_VSID_KP ASM_CONST(0x0000000000000400)
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#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
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#define SLB_VSID_L ASM_CONST(0x0000000000000100)
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#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
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#define SLB_VSID_LP ASM_CONST(0x0000000000000030)
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#define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
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#define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
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#define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
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#define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
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#define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
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#define SLB_VSID_KERNEL (SLB_VSID_KP)
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#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
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#define SLBIE_C (0x08000000)
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#define SLBIE_SSIZE_SHIFT 25
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/*
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* Hash table
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*/
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#define HPTES_PER_GROUP 8
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#define HPTE_V_SSIZE_SHIFT 62
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#define HPTE_V_AVPN_SHIFT 7
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#define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
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#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
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#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
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#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
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#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
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#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
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#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
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#define HPTE_V_VALID ASM_CONST(0x0000000000000001)
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#define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
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#define HPTE_R_TS ASM_CONST(0x4000000000000000)
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#define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000)
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#define HPTE_R_RPN_SHIFT 12
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#define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000)
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#define HPTE_R_PP ASM_CONST(0x0000000000000003)
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#define HPTE_R_N ASM_CONST(0x0000000000000004)
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#define HPTE_R_G ASM_CONST(0x0000000000000008)
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#define HPTE_R_M ASM_CONST(0x0000000000000010)
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#define HPTE_R_I ASM_CONST(0x0000000000000020)
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#define HPTE_R_W ASM_CONST(0x0000000000000040)
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#define HPTE_R_WIMG ASM_CONST(0x0000000000000078)
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#define HPTE_R_C ASM_CONST(0x0000000000000080)
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#define HPTE_R_R ASM_CONST(0x0000000000000100)
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#define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00)
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#define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
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#define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
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/* Values for PP (assumes Ks=0, Kp=1) */
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#define PP_RWXX 0 /* Supervisor read/write, User none */
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#define PP_RWRX 1 /* Supervisor read/write, User read */
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#define PP_RWRW 2 /* Supervisor read/write, User read/write */
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#define PP_RXRX 3 /* Supervisor read, User read */
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#define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */
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/* Fields for tlbiel instruction in architecture 2.06 */
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#define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */
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#define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */
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#define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */
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#define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */
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#define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */
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#define TLBIEL_INVAL_SET_SHIFT 12
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#define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
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#ifndef __ASSEMBLY__
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struct hash_pte {
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__be64 v;
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__be64 r;
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};
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extern struct hash_pte *htab_address;
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extern unsigned long htab_size_bytes;
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extern unsigned long htab_hash_mask;
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/*
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* Page size definition
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*
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* shift : is the "PAGE_SHIFT" value for that page size
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* sllp : is a bit mask with the value of SLB L || LP to be or'ed
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* directly to a slbmte "vsid" value
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* penc : is the HPTE encoding mask for the "LP" field:
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*
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*/
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struct mmu_psize_def
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{
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unsigned int shift; /* number of bits */
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int penc[MMU_PAGE_COUNT]; /* HPTE encoding */
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unsigned int tlbiel; /* tlbiel supported for that page size */
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unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
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unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
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};
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extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
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static inline int shift_to_mmu_psize(unsigned int shift)
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{
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int psize;
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for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
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if (mmu_psize_defs[psize].shift == shift)
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return psize;
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return -1;
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}
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static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
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{
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if (mmu_psize_defs[mmu_psize].shift)
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return mmu_psize_defs[mmu_psize].shift;
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BUG();
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}
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#endif /* __ASSEMBLY__ */
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/*
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* Segment sizes.
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* These are the values used by hardware in the B field of
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* SLB entries and the first dword of MMU hashtable entries.
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* The B field is 2 bits; the values 2 and 3 are unused and reserved.
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*/
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#define MMU_SEGSIZE_256M 0
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#define MMU_SEGSIZE_1T 1
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/*
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* encode page number shift.
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* in order to fit the 78 bit va in a 64 bit variable we shift the va by
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* 12 bits. This enable us to address upto 76 bit va.
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* For hpt hash from a va we can ignore the page size bits of va and for
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* hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
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* we work in all cases including 4k page size.
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*/
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#define VPN_SHIFT 12
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/*
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* HPTE Large Page (LP) details
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*/
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#define LP_SHIFT 12
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#define LP_BITS 8
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#define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT)
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#ifndef __ASSEMBLY__
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static inline int segment_shift(int ssize)
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{
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if (ssize == MMU_SEGSIZE_256M)
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return SID_SHIFT;
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return SID_SHIFT_1T;
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}
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/*
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* The current system page and segment sizes
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*/
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extern int mmu_linear_psize;
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extern int mmu_virtual_psize;
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extern int mmu_vmalloc_psize;
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extern int mmu_vmemmap_psize;
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extern int mmu_io_psize;
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extern int mmu_kernel_ssize;
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extern int mmu_highuser_ssize;
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extern u16 mmu_slb_size;
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extern unsigned long tce_alloc_start, tce_alloc_end;
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/*
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* If the processor supports 64k normal pages but not 64k cache
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* inhibited pages, we have to be prepared to switch processes
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* to use 4k pages when they create cache-inhibited mappings.
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* If this is the case, mmu_ci_restrictions will be set to 1.
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*/
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extern int mmu_ci_restrictions;
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/*
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* This computes the AVPN and B fields of the first dword of a HPTE,
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* for use when we want to match an existing PTE. The bottom 7 bits
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* of the returned value are zero.
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*/
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static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
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int ssize)
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{
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unsigned long v;
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/*
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* The AVA field omits the low-order 23 bits of the 78 bits VA.
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* These bits are not needed in the PTE, because the
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* low-order b of these bits are part of the byte offset
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* into the virtual page and, if b < 23, the high-order
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* 23-b of these bits are always used in selecting the
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* PTEGs to be searched
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*/
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v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
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v <<= HPTE_V_AVPN_SHIFT;
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v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
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return v;
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}
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/*
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* This function sets the AVPN and L fields of the HPTE appropriately
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* using the base page size and actual page size.
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*/
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static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize,
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int actual_psize, int ssize)
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{
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unsigned long v;
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v = hpte_encode_avpn(vpn, base_psize, ssize);
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if (actual_psize != MMU_PAGE_4K)
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v |= HPTE_V_LARGE;
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return v;
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}
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/*
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* This function sets the ARPN, and LP fields of the HPTE appropriately
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* for the page size. We assume the pa is already "clean" that is properly
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* aligned for the requested page size
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*/
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static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize,
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int actual_psize)
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{
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/* A 4K page needs no special encoding */
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if (actual_psize == MMU_PAGE_4K)
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return pa & HPTE_R_RPN;
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else {
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unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize];
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unsigned int shift = mmu_psize_defs[actual_psize].shift;
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return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT);
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}
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}
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/*
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* Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
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*/
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static inline unsigned long hpt_vpn(unsigned long ea,
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unsigned long vsid, int ssize)
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{
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unsigned long mask;
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int s_shift = segment_shift(ssize);
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mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
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return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
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}
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/*
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* This hashes a virtual address
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*/
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static inline unsigned long hpt_hash(unsigned long vpn,
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unsigned int shift, int ssize)
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{
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int mask;
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unsigned long hash, vsid;
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/* VPN_SHIFT can be atmost 12 */
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if (ssize == MMU_SEGSIZE_256M) {
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mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
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hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
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((vpn & mask) >> (shift - VPN_SHIFT));
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} else {
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mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
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vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
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hash = vsid ^ (vsid << 25) ^
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((vpn & mask) >> (shift - VPN_SHIFT)) ;
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}
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return hash & 0x7fffffffffUL;
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}
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extern int __hash_page_4K(unsigned long ea, unsigned long access,
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unsigned long vsid, pte_t *ptep, unsigned long trap,
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unsigned int local, int ssize, int subpage_prot);
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extern int __hash_page_64K(unsigned long ea, unsigned long access,
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unsigned long vsid, pte_t *ptep, unsigned long trap,
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unsigned int local, int ssize);
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struct mm_struct;
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unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
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extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
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int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
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pte_t *ptep, unsigned long trap, int local, int ssize,
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unsigned int shift, unsigned int mmu_psize);
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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extern int __hash_page_thp(unsigned long ea, unsigned long access,
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unsigned long vsid, pmd_t *pmdp, unsigned long trap,
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int local, int ssize, unsigned int psize);
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#else
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static inline int __hash_page_thp(unsigned long ea, unsigned long access,
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unsigned long vsid, pmd_t *pmdp,
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unsigned long trap, int local,
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int ssize, unsigned int psize)
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{
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BUG();
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return -1;
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}
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#endif
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extern void hash_failure_debug(unsigned long ea, unsigned long access,
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unsigned long vsid, unsigned long trap,
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int ssize, int psize, int lpsize,
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unsigned long pte);
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extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
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unsigned long pstart, unsigned long prot,
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int psize, int ssize);
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int htab_remove_mapping(unsigned long vstart, unsigned long vend,
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int psize, int ssize);
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extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
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extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
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extern void hpte_init_native(void);
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extern void hpte_init_lpar(void);
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extern void hpte_init_beat(void);
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extern void hpte_init_beat_v3(void);
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extern void slb_initialize(void);
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extern void slb_flush_and_rebolt(void);
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extern void slb_vmalloc_update(void);
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extern void slb_set_size(u16 size);
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#endif /* __ASSEMBLY__ */
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/*
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* VSID allocation (256MB segment)
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*
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* We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated
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* from mmu context id and effective segment id of the address.
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*
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* For user processes max context id is limited to ((1ul << 19) - 5)
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* for kernel space, we use the top 4 context ids to map address as below
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* NOTE: each context only support 64TB now.
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* 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ]
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* 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ]
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* 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ]
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* 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ]
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*
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* The proto-VSIDs are then scrambled into real VSIDs with the
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* multiplicative hash:
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*
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* VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
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*
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* VSID_MULTIPLIER is prime, so in particular it is
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* co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
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* Because the modulus is 2^n-1 we can compute it efficiently without
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* a divide or extra multiply (see below). The scramble function gives
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* robust scattering in the hash table (at least based on some initial
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* results).
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*
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* We also consider VSID 0 special. We use VSID 0 for slb entries mapping
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* bad address. This enables us to consolidate bad address handling in
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* hash_page.
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*
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* We also need to avoid the last segment of the last context, because that
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* would give a protovsid of 0x1fffffffff. That will result in a VSID 0
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* because of the modulo operation in vsid scramble. But the vmemmap
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* (which is what uses region 0xf) will never be close to 64TB in size
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* (it's 56 bytes per page of system memory).
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*/
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#define CONTEXT_BITS 19
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#define ESID_BITS 18
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#define ESID_BITS_1T 6
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/*
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* 256MB segment
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* The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments
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* available for user + kernel mapping. The top 4 contexts are used for
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* kernel mapping. Each segment contains 2^28 bytes. Each
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* context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts
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* (19 == 37 + 28 - 46).
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*/
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#define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 5)
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/*
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* This should be computed such that protovosid * vsid_mulitplier
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* doesn't overflow 64 bits. It should also be co-prime to vsid_modulus
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*/
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#define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */
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#define VSID_BITS_256M (CONTEXT_BITS + ESID_BITS)
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#define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
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#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
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#define VSID_BITS_1T (CONTEXT_BITS + ESID_BITS_1T)
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#define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
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#define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT))
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/*
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* This macro generates asm code to compute the VSID scramble
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* function. Used in slb_allocate() and do_stab_bolted. The function
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* computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
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*
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* rt = register continaing the proto-VSID and into which the
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* VSID will be stored
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* rx = scratch register (clobbered)
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*
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* - rt and rx must be different registers
|
|
* - The answer will end up in the low VSID_BITS bits of rt. The higher
|
|
* bits may contain other garbage, so you may need to mask the
|
|
* result.
|
|
*/
|
|
#define ASM_VSID_SCRAMBLE(rt, rx, size) \
|
|
lis rx,VSID_MULTIPLIER_##size@h; \
|
|
ori rx,rx,VSID_MULTIPLIER_##size@l; \
|
|
mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
|
|
\
|
|
srdi rx,rt,VSID_BITS_##size; \
|
|
clrldi rt,rt,(64-VSID_BITS_##size); \
|
|
add rt,rt,rx; /* add high and low bits */ \
|
|
/* NOTE: explanation based on VSID_BITS_##size = 36 \
|
|
* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
|
|
* 2^36-1+2^28-1. That in particular means that if r3 >= \
|
|
* 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
|
|
* the bit clear, r3 already has the answer we want, if it \
|
|
* doesn't, the answer is the low 36 bits of r3+1. So in all \
|
|
* cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
|
|
addi rx,rt,1; \
|
|
srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
|
|
add rt,rt,rx
|
|
|
|
/* 4 bits per slice and we have one slice per 1TB */
|
|
#define SLICE_ARRAY_SIZE (PGTABLE_RANGE >> 41)
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
#ifdef CONFIG_PPC_SUBPAGE_PROT
|
|
/*
|
|
* For the sub-page protection option, we extend the PGD with one of
|
|
* these. Basically we have a 3-level tree, with the top level being
|
|
* the protptrs array. To optimize speed and memory consumption when
|
|
* only addresses < 4GB are being protected, pointers to the first
|
|
* four pages of sub-page protection words are stored in the low_prot
|
|
* array.
|
|
* Each page of sub-page protection words protects 1GB (4 bytes
|
|
* protects 64k). For the 3-level tree, each page of pointers then
|
|
* protects 8TB.
|
|
*/
|
|
struct subpage_prot_table {
|
|
unsigned long maxaddr; /* only addresses < this are protected */
|
|
unsigned int **protptrs[(TASK_SIZE_USER64 >> 43)];
|
|
unsigned int *low_prot[4];
|
|
};
|
|
|
|
#define SBP_L1_BITS (PAGE_SHIFT - 2)
|
|
#define SBP_L2_BITS (PAGE_SHIFT - 3)
|
|
#define SBP_L1_COUNT (1 << SBP_L1_BITS)
|
|
#define SBP_L2_COUNT (1 << SBP_L2_BITS)
|
|
#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
|
|
#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
|
|
|
|
extern void subpage_prot_free(struct mm_struct *mm);
|
|
extern void subpage_prot_init_new_context(struct mm_struct *mm);
|
|
#else
|
|
static inline void subpage_prot_free(struct mm_struct *mm) {}
|
|
static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
|
|
#endif /* CONFIG_PPC_SUBPAGE_PROT */
|
|
|
|
typedef unsigned long mm_context_id_t;
|
|
struct spinlock;
|
|
|
|
typedef struct {
|
|
mm_context_id_t id;
|
|
u16 user_psize; /* page size index */
|
|
|
|
#ifdef CONFIG_PPC_MM_SLICES
|
|
u64 low_slices_psize; /* SLB page size encodings */
|
|
unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
|
|
#else
|
|
u16 sllp; /* SLB page size encoding */
|
|
#endif
|
|
unsigned long vdso_base;
|
|
#ifdef CONFIG_PPC_SUBPAGE_PROT
|
|
struct subpage_prot_table spt;
|
|
#endif /* CONFIG_PPC_SUBPAGE_PROT */
|
|
#ifdef CONFIG_PPC_ICSWX
|
|
struct spinlock *cop_lockp; /* guard acop and cop_pid */
|
|
unsigned long acop; /* mask of enabled coprocessor types */
|
|
unsigned int cop_pid; /* pid value used with coprocessors */
|
|
#endif /* CONFIG_PPC_ICSWX */
|
|
#ifdef CONFIG_PPC_64K_PAGES
|
|
/* for 4K PTE fragment support */
|
|
void *pte_frag;
|
|
#endif
|
|
} mm_context_t;
|
|
|
|
|
|
#if 0
|
|
/*
|
|
* The code below is equivalent to this function for arguments
|
|
* < 2^VSID_BITS, which is all this should ever be called
|
|
* with. However gcc is not clever enough to compute the
|
|
* modulus (2^n-1) without a second multiply.
|
|
*/
|
|
#define vsid_scramble(protovsid, size) \
|
|
((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
|
|
|
|
#else /* 1 */
|
|
#define vsid_scramble(protovsid, size) \
|
|
({ \
|
|
unsigned long x; \
|
|
x = (protovsid) * VSID_MULTIPLIER_##size; \
|
|
x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
|
|
(x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
|
|
})
|
|
#endif /* 1 */
|
|
|
|
/* Returns the segment size indicator for a user address */
|
|
static inline int user_segment_size(unsigned long addr)
|
|
{
|
|
/* Use 1T segments if possible for addresses >= 1T */
|
|
if (addr >= (1UL << SID_SHIFT_1T))
|
|
return mmu_highuser_ssize;
|
|
return MMU_SEGSIZE_256M;
|
|
}
|
|
|
|
static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
|
|
int ssize)
|
|
{
|
|
/*
|
|
* Bad address. We return VSID 0 for that
|
|
*/
|
|
if ((ea & ~REGION_MASK) >= PGTABLE_RANGE)
|
|
return 0;
|
|
|
|
if (ssize == MMU_SEGSIZE_256M)
|
|
return vsid_scramble((context << ESID_BITS)
|
|
| (ea >> SID_SHIFT), 256M);
|
|
return vsid_scramble((context << ESID_BITS_1T)
|
|
| (ea >> SID_SHIFT_1T), 1T);
|
|
}
|
|
|
|
/*
|
|
* This is only valid for addresses >= PAGE_OFFSET
|
|
*
|
|
* For kernel space, we use the top 4 context ids to map address as below
|
|
* 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ]
|
|
* 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ]
|
|
* 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ]
|
|
* 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ]
|
|
*/
|
|
static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
|
|
{
|
|
unsigned long context;
|
|
|
|
/*
|
|
* kernel take the top 4 context from the available range
|
|
*/
|
|
context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1;
|
|
return get_vsid(context, ea, ssize);
|
|
}
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
#endif /* _ASM_POWERPC_MMU_HASH64_H_ */
|