Shukun Tan de3daf4b4a crypto: hisilicon - Configure zip RAS error type ... Configure zip RAS error type in error handle initialization, Where ECC 1bit is configured as CE error, others are NFE. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>		2020-02-13 16:58:08 +08:00
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hpre	crypto: hisilicon - Unify hardware error init/uninit into QM	2020-02-13 16:58:08 +08:00
sec	crypto: hisilicon - Matching the dma address for dma_pool_free()	2019-09-20 22:53:09 +10:00
sec2	crypto: hisilicon - Unify hardware error init/uninit into QM	2020-02-13 16:58:08 +08:00
zip	crypto: hisilicon - Configure zip RAS error type	2020-02-13 16:58:08 +08:00
Kconfig	crypto: hisilicon - Add aead support on SEC2	2020-01-16 15:18:15 +08:00
Makefile	crypto: hisilicon - add HiSilicon SEC V2 driver	2019-11-22 18:48:36 +08:00
qm.c	crypto: hisilicon - Unify hardware error init/uninit into QM	2020-02-13 16:58:08 +08:00
qm.h	crypto: hisilicon - Unify hardware error init/uninit into QM	2020-02-13 16:58:08 +08:00
sgl.c	crypto: hisilicon - Remove useless MODULE macros	2019-12-11 16:34:45 +08:00