forked from Minki/linux
22c21003a9
Lemote Loongson 2F family machines use CS5536 as their south bridge and need these lowlevel interfaces to access the devices on CS5536. Virtualize the legacy devices on CS5536 as PCI devices. This way users can access the CS5536 PCI config space directly as a normal multi-function PCI 2.2 device. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: zhangfx@lemote.com Cc: yanh@lemote.com Cc: huhb@lemote.com Cc: Nicholas Mc Guire <hofrat@hofr.at> Cc: Arnaud Patard <apatard@mandriva.com> Cc: loongson-dev@googlegroups.com Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
154 lines
3.9 KiB
C
154 lines
3.9 KiB
C
/*
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* the definition file of cs5536 Virtual Support Module(VSM).
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* pci configuration space can be accessed through the VSM, so
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* there is no need of the MSR read/write now, except the spec.
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* MSR registers which are not implemented yet.
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*
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* Copyright (C) 2007 Lemote Inc.
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* Author : jlliu, liujl@lemote.com
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*/
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#ifndef _CS5536_PCI_H
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#define _CS5536_PCI_H
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#include <linux/types.h>
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#include <linux/pci_regs.h>
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extern void cs5536_pci_conf_write4(int function, int reg, u32 value);
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extern u32 cs5536_pci_conf_read4(int function, int reg);
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#define CS5536_ACC_INTR 9
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#define CS5536_IDE_INTR 14
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#define CS5536_USB_INTR 11
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#define CS5536_MFGPT_INTR 5
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#define CS5536_UART1_INTR 4
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#define CS5536_UART2_INTR 3
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/************** PCI BUS DEVICE FUNCTION ***************/
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/*
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* PCI bus device function
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*/
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#define PCI_BUS_CS5536 0
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#define PCI_IDSEL_CS5536 14
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/********** STANDARD PCI-2.2 EXPANSION ****************/
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/*
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* PCI configuration space
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* we have to virtualize the PCI configure space head, so we should
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* define the necessary IDs and some others.
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*/
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/* CONFIG of PCI VENDOR ID*/
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#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \
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(((mod_dev_id) << 16) | (sys_vendor_id))
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/* VENDOR ID */
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#define CS5536_VENDOR_ID 0x1022
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/* DEVICE ID */
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#define CS5536_ISA_DEVICE_ID 0x2090
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#define CS5536_IDE_DEVICE_ID 0x209a
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#define CS5536_ACC_DEVICE_ID 0x2093
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#define CS5536_OHCI_DEVICE_ID 0x2094
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#define CS5536_EHCI_DEVICE_ID 0x2095
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/* CLASS CODE : CLASS SUB-CLASS INTERFACE */
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#define CS5536_ISA_CLASS_CODE 0x060100
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#define CS5536_IDE_CLASS_CODE 0x010180
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#define CS5536_ACC_CLASS_CODE 0x040100
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#define CS5536_OHCI_CLASS_CODE 0x0C0310
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#define CS5536_EHCI_CLASS_CODE 0x0C0320
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/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */
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#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer) \
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((PCI_NONE_BIST << 24) | ((header_type) << 16) \
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| ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE);
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#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */
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#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */
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#define PCI_NORMAL_HEADER_TYPE 0x00
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#define PCI_NORMAL_LATENCY_TIMER 0x00
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#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */
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/* BAR */
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#define PCI_BAR0_REG 0x10
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#define PCI_BAR1_REG 0x14
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#define PCI_BAR2_REG 0x18
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#define PCI_BAR3_REG 0x1c
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#define PCI_BAR4_REG 0x20
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#define PCI_BAR5_REG 0x24
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#define PCI_BAR_COUNT 6
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#define PCI_BAR_RANGE_MASK 0xFFFFFFFF
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/* CARDBUS CIS POINTER */
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#define PCI_CARDBUS_CIS_POINTER 0x00000000
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/* SUBSYSTEM VENDOR ID */
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#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID
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/* SUBSYSTEM ID */
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#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID
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#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID
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#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID
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#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID
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#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID
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/* EXPANSION ROM BAR */
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#define PCI_EXPANSION_ROM_BAR 0x00000000
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/* CAPABILITIES POINTER */
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#define PCI_CAPLIST_POINTER 0x00000000
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#define PCI_CAPLIST_USB_POINTER 0x40
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/* INTERRUPT */
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#define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \
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((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \
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((pin) << 8) | (mod_intr))
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#define PCI_MAX_LATENCY 0x40
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#define PCI_MIN_GRANT 0x00
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#define PCI_DEFAULT_PIN 0x01
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/*********** EXPANSION PCI REG ************************/
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/*
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* ISA EXPANSION
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*/
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#define PCI_UART1_INT_REG 0x50
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#define PCI_UART2_INT_REG 0x54
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#define PCI_ISA_FIXUP_REG 0x58
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/*
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* IDE EXPANSION
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*/
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#define PCI_IDE_CFG_REG 0x40
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#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF
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#define PCI_IDE_DTC_REG 0x48
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#define PCI_IDE_CAST_REG 0x4C
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#define PCI_IDE_ETC_REG 0x50
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#define PCI_IDE_PM_REG 0x54
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#define PCI_IDE_INT_REG 0x60
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/*
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* ACC EXPANSION
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*/
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#define PCI_ACC_INT_REG 0x50
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/*
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* OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI
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*/
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#define PCI_OHCI_PM_REG 0x40
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#define PCI_OHCI_INT_REG 0x50
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/*
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* EHCI EXPANSION
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*/
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#define PCI_EHCI_LEGSMIEN_REG 0x50
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#define PCI_EHCI_LEGSMISTS_REG 0x54
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#define PCI_EHCI_FLADJ_REG 0x60
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#endif /* _CS5536_PCI_H_ */
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