forked from Minki/linux
dd135095a8
Since PWMs are only useful if they are actually connected to an output pin,
let users enable them explicitly in their device trees where they should
also set up the pin configuration. This is in sync with a recent change
(commit e2675266b3 "ARM: dts: imx6qdl: disable PWMs by default")
to other i.MX SoCs.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
760 lines
20 KiB
Plaintext
760 lines
20 KiB
Plaintext
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/clock/imx6ul-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "imx6ul-pinfunc.h"
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#include "skeleton.dtsi"
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/ {
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aliases {
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ethernet0 = &fec1;
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ethernet1 = &fec2;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &uart6;
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serial6 = &uart7;
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serial7 = &uart8;
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spi0 = &ecspi1;
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spi1 = &ecspi2;
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spi2 = &ecspi3;
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spi3 = &ecspi4;
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usbphy0 = &usbphy1;
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usbphy1 = &usbphy2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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clock-latency = <61036>; /* two CLK32 periods */
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operating-points = <
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/* kHz uV */
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528000 1250000
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396000 1150000
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198000 1150000
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>;
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fsl,soc-operating-points = <
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/* KHz uV */
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528000 1250000
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396000 1150000
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198000 1150000
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>;
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clocks = <&clks IMX6UL_CLK_ARM>,
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<&clks IMX6UL_CLK_PLL2_BUS>,
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<&clks IMX6UL_CLK_PLL2_PFD2>,
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<&clks IMX6UL_CA7_SECONDARY_SEL>,
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<&clks IMX6UL_CLK_STEP>,
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<&clks IMX6UL_CLK_PLL1_SW>,
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<&clks IMX6UL_CLK_PLL1_SYS>,
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<&clks IMX6UL_PLL1_BYPASS>,
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<&clks IMX6UL_CLK_PLL1>,
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<&clks IMX6UL_PLL1_BYPASS_SRC>,
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<&clks IMX6UL_CLK_OSC>;
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clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
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"secondary_sel", "step", "pll1_sw",
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"pll1_sys", "pll1_bypass", "pll1",
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"pll1_bypass_src", "osc";
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arm-supply = <®_arm>;
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soc-supply = <®_soc>;
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};
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};
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intc: interrupt-controller@00a01000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00a01000 0x1000>,
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<0x00a02000 0x1000>,
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<0x00a04000 0x2000>,
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<0x00a06000 0x2000>;
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};
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ckil: clock-cli {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "ckil";
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};
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osc: clock-osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "osc";
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};
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ipp_di0: clock-di0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "ipp_di0";
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};
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ipp_di1: clock-di1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "ipp_di1";
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gpc>;
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ranges;
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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ocram: sram@00900000 {
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compatible = "mmio-sram";
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reg = <0x00900000 0x20000>;
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};
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aips1: aips-bus@02000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x02000000 0x100000>;
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ranges;
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spba-bus@02000000 {
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x02000000 0x40000>;
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ranges;
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ecspi1: ecspi@02008000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
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reg = <0x02008000 0x4000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_ECSPI1>,
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<&clks IMX6UL_CLK_ECSPI1>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ecspi2: ecspi@0200c000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
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reg = <0x0200c000 0x4000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_ECSPI2>,
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<&clks IMX6UL_CLK_ECSPI2>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ecspi3: ecspi@02010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
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reg = <0x02010000 0x4000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_ECSPI3>,
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<&clks IMX6UL_CLK_ECSPI3>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ecspi4: ecspi@02014000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
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reg = <0x02014000 0x4000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_ECSPI4>,
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<&clks IMX6UL_CLK_ECSPI4>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart7: serial@02018000 {
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compatible = "fsl,imx6ul-uart",
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"fsl,imx6q-uart";
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reg = <0x02018000 0x4000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_UART7_IPG>,
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<&clks IMX6UL_CLK_UART7_SERIAL>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart1: serial@02020000 {
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compatible = "fsl,imx6ul-uart",
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"fsl,imx6q-uart";
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reg = <0x02020000 0x4000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_UART1_IPG>,
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<&clks IMX6UL_CLK_UART1_SERIAL>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart8: serial@02024000 {
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compatible = "fsl,imx6ul-uart",
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"fsl,imx6q-uart";
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reg = <0x02024000 0x4000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_UART8_IPG>,
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<&clks IMX6UL_CLK_UART8_SERIAL>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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};
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tsc: tsc@02040000 {
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compatible = "fsl,imx6ul-tsc";
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reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_IPG>,
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<&clks IMX6UL_CLK_ADC2>;
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clock-names = "tsc", "adc";
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status = "disabled";
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};
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gpt1: gpt@02098000 {
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compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
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reg = <0x02098000 0x4000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
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<&clks IMX6UL_CLK_GPT1_SERIAL>;
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clock-names = "ipg", "per";
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};
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gpio1: gpio@0209c000 {
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compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
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reg = <0x0209c000 0x4000>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@020a0000 {
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compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
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reg = <0x020a0000 0x4000>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@020a4000 {
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compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
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reg = <0x020a4000 0x4000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@020a8000 {
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compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
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reg = <0x020a8000 0x4000>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio5: gpio@020ac000 {
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compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
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reg = <0x020ac000 0x4000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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fec2: ethernet@020b4000 {
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compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
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reg = <0x020b4000 0x4000>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_ENET>,
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<&clks IMX6UL_CLK_ENET_AHB>,
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<&clks IMX6UL_CLK_ENET_PTP>,
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<&clks IMX6UL_CLK_ENET2_REF_125M>,
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<&clks IMX6UL_CLK_ENET2_REF_125M>;
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clock-names = "ipg", "ahb", "ptp",
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"enet_clk_ref", "enet_out";
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fsl,num-tx-queues=<1>;
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fsl,num-rx-queues=<1>;
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status = "disabled";
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};
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wdog1: wdog@020bc000 {
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compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
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reg = <0x020bc000 0x4000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_WDOG1>;
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};
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wdog2: wdog@020c0000 {
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compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
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reg = <0x020c0000 0x4000>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_WDOG2>;
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status = "disabled";
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};
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clks: ccm@020c4000 {
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compatible = "fsl,imx6ul-ccm";
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reg = <0x020c4000 0x4000>;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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#clock-cells = <1>;
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clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
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clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
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};
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anatop: anatop@020c8000 {
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compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
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"syscon", "simple-bus";
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reg = <0x020c8000 0x1000>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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reg_3p0: regulator-3p0@120 {
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compatible = "fsl,anatop-regulator";
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regulator-name = "vdd3p0";
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regulator-min-microvolt = <2625000>;
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regulator-max-microvolt = <3400000>;
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anatop-reg-offset = <0x120>;
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anatop-vol-bit-shift = <8>;
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anatop-vol-bit-width = <5>;
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anatop-min-bit-val = <0>;
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anatop-min-voltage = <2625000>;
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anatop-max-voltage = <3400000>;
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anatop-enable-bit = <0>;
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};
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reg_arm: regulator-vddcore@140 {
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compatible = "fsl,anatop-regulator";
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regulator-name = "cpu";
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regulator-min-microvolt = <725000>;
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regulator-max-microvolt = <1450000>;
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regulator-always-on;
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anatop-reg-offset = <0x140>;
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anatop-vol-bit-shift = <0>;
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anatop-vol-bit-width = <5>;
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anatop-delay-reg-offset = <0x170>;
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anatop-delay-bit-shift = <24>;
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anatop-delay-bit-width = <2>;
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anatop-min-bit-val = <1>;
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anatop-min-voltage = <725000>;
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anatop-max-voltage = <1450000>;
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};
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reg_soc: regulator-vddsoc@140 {
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compatible = "fsl,anatop-regulator";
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regulator-name = "vddsoc";
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regulator-min-microvolt = <725000>;
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regulator-max-microvolt = <1450000>;
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regulator-always-on;
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anatop-reg-offset = <0x140>;
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anatop-vol-bit-shift = <18>;
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anatop-vol-bit-width = <5>;
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anatop-delay-reg-offset = <0x170>;
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anatop-delay-bit-shift = <28>;
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anatop-delay-bit-width = <2>;
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anatop-min-bit-val = <1>;
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anatop-min-voltage = <725000>;
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anatop-max-voltage = <1450000>;
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};
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};
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usbphy1: usbphy@020c9000 {
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compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
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reg = <0x020c9000 0x1000>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_USBPHY1>;
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phy-3p0-supply = <®_3p0>;
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fsl,anatop = <&anatop>;
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};
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usbphy2: usbphy@020ca000 {
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compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
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reg = <0x020ca000 0x1000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_USBPHY2>;
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phy-3p0-supply = <®_3p0>;
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fsl,anatop = <&anatop>;
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};
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snvs: snvs@020cc000 {
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compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
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reg = <0x020cc000 0x4000>;
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snvs_rtc: snvs-rtc-lp {
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compatible = "fsl,sec-v4.0-mon-rtc-lp";
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regmap = <&snvs>;
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offset = <0x34>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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};
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snvs_poweroff: snvs-poweroff {
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compatible = "syscon-poweroff";
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regmap = <&snvs>;
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offset = <0x38>;
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mask = <0x60>;
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status = "disabled";
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};
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snvs_pwrkey: snvs-powerkey {
|
|
compatible = "fsl,sec-v4.0-pwrkey";
|
|
regmap = <&snvs>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
linux,keycode = <KEY_POWER>;
|
|
wakeup-source;
|
|
};
|
|
};
|
|
|
|
epit1: epit@020d0000 {
|
|
reg = <0x020d0000 0x4000>;
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
epit2: epit@020d4000 {
|
|
reg = <0x020d4000 0x4000>;
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
src: src@020d8000 {
|
|
compatible = "fsl,imx6ul-src", "fsl,imx51-src";
|
|
reg = <0x020d8000 0x4000>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpc: gpc@020dc000 {
|
|
compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
|
|
reg = <0x020dc000 0x4000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-parent = <&intc>;
|
|
};
|
|
|
|
iomuxc: iomuxc@020e0000 {
|
|
compatible = "fsl,imx6ul-iomuxc";
|
|
reg = <0x020e0000 0x4000>;
|
|
};
|
|
|
|
gpr: iomuxc-gpr@020e4000 {
|
|
compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
|
|
reg = <0x020e4000 0x4000>;
|
|
};
|
|
|
|
gpt2: gpt@020e8000 {
|
|
compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
|
|
reg = <0x020e8000 0x4000>;
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
|
|
<&clks IMX6UL_CLK_GPT2_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
pwm5: pwm@020f0000 {
|
|
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
|
|
reg = <0x020f0000 0x4000>;
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_PWM5>,
|
|
<&clks IMX6UL_CLK_PWM5>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm6: pwm@020f4000 {
|
|
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
|
|
reg = <0x020f4000 0x4000>;
|
|
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_PWM6>,
|
|
<&clks IMX6UL_CLK_PWM6>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm7: pwm@020f8000 {
|
|
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
|
|
reg = <0x020f8000 0x4000>;
|
|
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_PWM7>,
|
|
<&clks IMX6UL_CLK_PWM7>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm8: pwm@020fc000 {
|
|
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
|
|
reg = <0x020fc000 0x4000>;
|
|
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_PWM8>,
|
|
<&clks IMX6UL_CLK_PWM8>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
aips2: aips-bus@02100000 {
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x02100000 0x100000>;
|
|
ranges;
|
|
|
|
usbotg1: usb@02184000 {
|
|
compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
|
|
reg = <0x02184000 0x200>;
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_USBOH3>;
|
|
fsl,usbphy = <&usbphy1>;
|
|
fsl,usbmisc = <&usbmisc 0>;
|
|
fsl,anatop = <&anatop>;
|
|
ahb-burst-config = <0x0>;
|
|
tx-burst-size-dword = <0x10>;
|
|
rx-burst-size-dword = <0x10>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbotg2: usb@02184200 {
|
|
compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
|
|
reg = <0x02184200 0x200>;
|
|
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_USBOH3>;
|
|
fsl,usbphy = <&usbphy2>;
|
|
fsl,usbmisc = <&usbmisc 1>;
|
|
ahb-burst-config = <0x0>;
|
|
tx-burst-size-dword = <0x10>;
|
|
rx-burst-size-dword = <0x10>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbmisc: usbmisc@02184800 {
|
|
#index-cells = <1>;
|
|
compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
|
|
reg = <0x02184800 0x200>;
|
|
};
|
|
|
|
fec1: ethernet@02188000 {
|
|
compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
|
|
reg = <0x02188000 0x4000>;
|
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_ENET>,
|
|
<&clks IMX6UL_CLK_ENET_AHB>,
|
|
<&clks IMX6UL_CLK_ENET_PTP>,
|
|
<&clks IMX6UL_CLK_ENET_REF>,
|
|
<&clks IMX6UL_CLK_ENET_REF>;
|
|
clock-names = "ipg", "ahb", "ptp",
|
|
"enet_clk_ref", "enet_out";
|
|
fsl,num-tx-queues=<1>;
|
|
fsl,num-rx-queues=<1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc1: usdhc@02190000 {
|
|
compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
|
|
reg = <0x02190000 0x4000>;
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_USDHC1>,
|
|
<&clks IMX6UL_CLK_USDHC1>,
|
|
<&clks IMX6UL_CLK_USDHC1>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc2: usdhc@02194000 {
|
|
compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
|
|
reg = <0x02194000 0x4000>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_USDHC2>,
|
|
<&clks IMX6UL_CLK_USDHC2>,
|
|
<&clks IMX6UL_CLK_USDHC2>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
adc1: adc@02198000 {
|
|
compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
|
|
reg = <0x02198000 0x4000>;
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_ADC1>;
|
|
num-channels = <2>;
|
|
clock-names = "adc";
|
|
fsl,adck-max-frequency = <30000000>, <40000000>,
|
|
<20000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@021a0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021a0000 0x4000>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_I2C1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@021a4000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021a4000 0x4000>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_I2C2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@021a8000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021a8000 0x4000>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_I2C3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmdc: mmdc@021b0000 {
|
|
compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
|
|
reg = <0x021b0000 0x4000>;
|
|
};
|
|
|
|
qspi: qspi@021e0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
|
|
reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
|
|
reg-names = "QuadSPI", "QuadSPI-memory";
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_QSPI>,
|
|
<&clks IMX6UL_CLK_QSPI>;
|
|
clock-names = "qspi_en", "qspi";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@021e8000 {
|
|
compatible = "fsl,imx6ul-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x021e8000 0x4000>;
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_UART2_IPG>,
|
|
<&clks IMX6UL_CLK_UART2_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@021ec000 {
|
|
compatible = "fsl,imx6ul-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x021ec000 0x4000>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_UART3_IPG>,
|
|
<&clks IMX6UL_CLK_UART3_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@021f0000 {
|
|
compatible = "fsl,imx6ul-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x021f0000 0x4000>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_UART4_IPG>,
|
|
<&clks IMX6UL_CLK_UART4_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@021f4000 {
|
|
compatible = "fsl,imx6ul-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x021f4000 0x4000>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_UART5_IPG>,
|
|
<&clks IMX6UL_CLK_UART5_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@021f8000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021f8000 0x4000>;
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_I2C4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart6: serial@021fc000 {
|
|
compatible = "fsl,imx6ul-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x021fc000 0x4000>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_UART6_IPG>,
|
|
<&clks IMX6UL_CLK_UART6_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|