dbd6654329
This patch adds support for THD_DEL (Data Hold Delay) to Cadence I3C master constoller driver. As per MIPI I3C Specification 1.0, Table 75 (page 142) defines non-zero minimal tHD_PP timing on master output (Fig 65). This setting allows to meet this timing on master's soc outputs, regardless of PCB balancing. Signed-off-by: Przemyslaw Gaj <pgaj@cadence.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> |
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| .. | ||
| master | ||
| device.c | ||
| internals.h | ||
| Kconfig | ||
| Makefile | ||
| master.c | ||