forked from Minki/linux
1acbdeb92c
Freescale DSPI module will have two endianess in different platform, but ARM is little endian. So when DSPI in big endian, core in little endian, readl and writel can not adjust R/W register in this condition. This patch will remove general readl/writel, and import regmap mechanism. Data endian will be transfered in regmap APIs. Documents: dspi add bool "big-endian" in dts node if DSPI module work in big endian. Signed-off-by: Chao Fu <b44548@freescale.com> Reviewed-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
45 lines
1.2 KiB
Plaintext
45 lines
1.2 KiB
Plaintext
ARM Freescale DSPI controller
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Required properties:
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- compatible : "fsl,vf610-dspi"
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- reg : Offset and length of the register set for the device
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- interrupts : Should contain SPI controller interrupt
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- clocks: from common clock binding: handle to dspi clock.
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- clock-names: from common clock binding: Shall be "dspi".
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- pinctrl-0: pin control group to be used for this controller.
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- pinctrl-names: must contain a "default" entry.
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- spi-num-chipselects : the number of the chipselect signals.
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- bus-num : the slave chip chipselect signal number.
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- big-endian : if DSPI modudle is big endian, the bool will be set in node.
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Example:
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dspi0@4002c000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,vf610-dspi";
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reg = <0x4002c000 0x1000>;
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interrupts = <0 67 0x04>;
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clocks = <&clks VF610_CLK_DSPI0>;
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clock-names = "dspi";
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spi-num-chipselects = <5>;
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bus-num = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dspi0_1>;
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big-endian;
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status = "okay";
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sflash: at26df081a@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,at26df081a";
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spi-max-frequency = <16000000>;
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spi-cpol;
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spi-cpha;
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reg = <0>;
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linux,modalias = "m25p80";
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modal = "at26df081a";
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};
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};
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