forked from Minki/linux
d7d4eeddb8
With the introduction of per-process GTT space, the hardware designers thought it wise to also limit the ability to write to MMIO space to only a "secure" batch buffer. The ability to rewrite registers is the only way to program the hardware to perform certain operations like scanline waits (required for tear-free windowed updates). So we either have a choice of adding an interface to perform those synchronized updates inside the kernel, or we permit certain processes the ability to write to the "safe" registers from within its command stream. This patch exposes the ability to submit a SECURE batch buffer to DRM_ROOT_ONLY|DRM_MASTER processes. v2: Haswell split up bit8 into a ppgtt bit (still bit8) and a security bit (bit 13, accidentally not set). Also add a comment explaining why secure batches need a global gtt binding. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> (v1) [danvet: added hsw fixup.] Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
232 lines
6.8 KiB
C
232 lines
6.8 KiB
C
#ifndef _INTEL_RINGBUFFER_H_
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#define _INTEL_RINGBUFFER_H_
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struct intel_hw_status_page {
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u32 *page_addr;
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unsigned int gfx_addr;
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struct drm_i915_gem_object *obj;
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};
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#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
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#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
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#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
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#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
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#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
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#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
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#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
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#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
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#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
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#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
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#define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
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#define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
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#define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
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struct intel_ring_buffer {
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const char *name;
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enum intel_ring_id {
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RCS = 0x0,
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VCS,
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BCS,
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} id;
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#define I915_NUM_RINGS 3
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u32 mmio_base;
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void __iomem *virtual_start;
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struct drm_device *dev;
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struct drm_i915_gem_object *obj;
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u32 head;
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u32 tail;
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int space;
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int size;
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int effective_size;
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struct intel_hw_status_page status_page;
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/** We track the position of the requests in the ring buffer, and
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* when each is retired we increment last_retired_head as the GPU
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* must have finished processing the request and so we know we
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* can advance the ringbuffer up to that position.
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*
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* last_retired_head is set to -1 after the value is consumed so
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* we can detect new retirements.
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*/
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u32 last_retired_head;
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u32 irq_refcount; /* protected by dev_priv->irq_lock */
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u32 irq_enable_mask; /* bitmask to enable ring interrupt */
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u32 trace_irq_seqno;
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u32 sync_seqno[I915_NUM_RINGS-1];
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bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
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void (*irq_put)(struct intel_ring_buffer *ring);
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int (*init)(struct intel_ring_buffer *ring);
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void (*write_tail)(struct intel_ring_buffer *ring,
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u32 value);
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int __must_check (*flush)(struct intel_ring_buffer *ring,
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u32 invalidate_domains,
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u32 flush_domains);
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int (*add_request)(struct intel_ring_buffer *ring,
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u32 *seqno);
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/* Some chipsets are not quite as coherent as advertised and need
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* an expensive kick to force a true read of the up-to-date seqno.
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* However, the up-to-date seqno is not always required and the last
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* seen value is good enough. Note that the seqno will always be
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* monotonic, even if not coherent.
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*/
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u32 (*get_seqno)(struct intel_ring_buffer *ring,
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bool lazy_coherency);
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int (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
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u32 offset, u32 length,
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unsigned flags);
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#define I915_DISPATCH_SECURE 0x1
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void (*cleanup)(struct intel_ring_buffer *ring);
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int (*sync_to)(struct intel_ring_buffer *ring,
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struct intel_ring_buffer *to,
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u32 seqno);
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u32 semaphore_register[3]; /*our mbox written by others */
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u32 signal_mbox[2]; /* mboxes this ring signals to */
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/**
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* List of objects currently involved in rendering from the
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* ringbuffer.
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*
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* Includes buffers having the contents of their GPU caches
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* flushed, not necessarily primitives. last_rendering_seqno
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* represents when the rendering involved will be completed.
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*
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* A reference is held on the buffer while on this list.
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*/
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struct list_head active_list;
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/**
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* List of breadcrumbs associated with GPU requests currently
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* outstanding.
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*/
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struct list_head request_list;
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/**
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* Do we have some not yet emitted requests outstanding?
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*/
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u32 outstanding_lazy_request;
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bool gpu_caches_dirty;
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wait_queue_head_t irq_queue;
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/**
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* Do an explicit TLB flush before MI_SET_CONTEXT
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*/
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bool itlb_before_ctx_switch;
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struct i915_hw_context *default_context;
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struct drm_i915_gem_object *last_context_obj;
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void *private;
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};
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static inline bool
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intel_ring_initialized(struct intel_ring_buffer *ring)
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{
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return ring->obj != NULL;
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}
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static inline unsigned
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intel_ring_flag(struct intel_ring_buffer *ring)
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{
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return 1 << ring->id;
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}
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static inline u32
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intel_ring_sync_index(struct intel_ring_buffer *ring,
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struct intel_ring_buffer *other)
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{
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int idx;
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/*
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* cs -> 0 = vcs, 1 = bcs
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* vcs -> 0 = bcs, 1 = cs,
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* bcs -> 0 = cs, 1 = vcs.
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*/
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idx = (other - ring) - 1;
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if (idx < 0)
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idx += I915_NUM_RINGS;
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return idx;
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}
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static inline u32
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intel_read_status_page(struct intel_ring_buffer *ring,
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int reg)
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{
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/* Ensure that the compiler doesn't optimize away the load. */
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barrier();
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return ring->status_page.page_addr[reg];
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}
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/**
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* Reads a dword out of the status page, which is written to from the command
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* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
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* MI_STORE_DATA_IMM.
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*
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* The following dwords have a reserved meaning:
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* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
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* 0x04: ring 0 head pointer
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* 0x05: ring 1 head pointer (915-class)
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* 0x06: ring 2 head pointer (915-class)
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* 0x10-0x1b: Context status DWords (GM45)
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* 0x1f: Last written status offset. (GM45)
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*
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* The area from dword 0x20 to 0x3ff is available for driver usage.
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*/
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#define I915_GEM_HWS_INDEX 0x20
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void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
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int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
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static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring)
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{
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return intel_wait_ring_buffer(ring, ring->size - 8);
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}
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int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
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static inline void intel_ring_emit(struct intel_ring_buffer *ring,
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u32 data)
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{
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iowrite32(data, ring->virtual_start + ring->tail);
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ring->tail += 4;
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}
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void intel_ring_advance(struct intel_ring_buffer *ring);
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u32 intel_ring_get_seqno(struct intel_ring_buffer *ring);
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int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
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int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
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int intel_init_render_ring_buffer(struct drm_device *dev);
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int intel_init_bsd_ring_buffer(struct drm_device *dev);
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int intel_init_blt_ring_buffer(struct drm_device *dev);
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u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
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void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
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static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
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{
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return ring->tail;
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}
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static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
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{
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if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
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ring->trace_irq_seqno = seqno;
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}
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/* DRI warts */
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int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
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#endif /* _INTEL_RINGBUFFER_H_ */
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