da3d378dec
Let dma_fence::signaled, etc, read directly from the address that the hw is writing with updated completed fence seqno, so we can potentially notice that the fence is signaled sooner. Plus add some docs. Signed-off-by: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20210726144359.2179302-2-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
146 lines
3.3 KiB
C
146 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013-2016 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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#include <linux/dma-fence.h>
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#include "msm_drv.h"
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#include "msm_fence.h"
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struct msm_fence_context *
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msm_fence_context_alloc(struct drm_device *dev, volatile uint32_t *fenceptr,
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const char *name)
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{
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struct msm_fence_context *fctx;
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fctx = kzalloc(sizeof(*fctx), GFP_KERNEL);
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if (!fctx)
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return ERR_PTR(-ENOMEM);
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fctx->dev = dev;
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strncpy(fctx->name, name, sizeof(fctx->name));
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fctx->context = dma_fence_context_alloc(1);
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fctx->fenceptr = fenceptr;
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init_waitqueue_head(&fctx->event);
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spin_lock_init(&fctx->spinlock);
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return fctx;
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}
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void msm_fence_context_free(struct msm_fence_context *fctx)
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{
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kfree(fctx);
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}
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static inline bool fence_completed(struct msm_fence_context *fctx, uint32_t fence)
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{
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/*
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* Note: Check completed_fence first, as fenceptr is in a write-combine
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* mapping, so it will be more expensive to read.
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*/
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return (int32_t)(fctx->completed_fence - fence) >= 0 ||
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(int32_t)(*fctx->fenceptr - fence) >= 0;
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}
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/* legacy path for WAIT_FENCE ioctl: */
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int msm_wait_fence(struct msm_fence_context *fctx, uint32_t fence,
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ktime_t *timeout, bool interruptible)
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{
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int ret;
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if (fence > fctx->last_fence) {
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DRM_ERROR_RATELIMITED("%s: waiting on invalid fence: %u (of %u)\n",
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fctx->name, fence, fctx->last_fence);
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return -EINVAL;
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}
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if (!timeout) {
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/* no-wait: */
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ret = fence_completed(fctx, fence) ? 0 : -EBUSY;
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} else {
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unsigned long remaining_jiffies = timeout_to_jiffies(timeout);
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if (interruptible)
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ret = wait_event_interruptible_timeout(fctx->event,
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fence_completed(fctx, fence),
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remaining_jiffies);
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else
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ret = wait_event_timeout(fctx->event,
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fence_completed(fctx, fence),
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remaining_jiffies);
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if (ret == 0) {
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DBG("timeout waiting for fence: %u (completed: %u)",
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fence, fctx->completed_fence);
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ret = -ETIMEDOUT;
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} else if (ret != -ERESTARTSYS) {
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ret = 0;
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}
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}
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return ret;
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}
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/* called from workqueue */
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void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence)
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{
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spin_lock(&fctx->spinlock);
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fctx->completed_fence = max(fence, fctx->completed_fence);
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spin_unlock(&fctx->spinlock);
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wake_up_all(&fctx->event);
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}
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struct msm_fence {
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struct dma_fence base;
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struct msm_fence_context *fctx;
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};
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static inline struct msm_fence *to_msm_fence(struct dma_fence *fence)
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{
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return container_of(fence, struct msm_fence, base);
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}
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static const char *msm_fence_get_driver_name(struct dma_fence *fence)
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{
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return "msm";
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}
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static const char *msm_fence_get_timeline_name(struct dma_fence *fence)
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{
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struct msm_fence *f = to_msm_fence(fence);
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return f->fctx->name;
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}
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static bool msm_fence_signaled(struct dma_fence *fence)
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{
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struct msm_fence *f = to_msm_fence(fence);
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return fence_completed(f->fctx, f->base.seqno);
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}
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static const struct dma_fence_ops msm_fence_ops = {
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.get_driver_name = msm_fence_get_driver_name,
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.get_timeline_name = msm_fence_get_timeline_name,
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.signaled = msm_fence_signaled,
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};
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struct dma_fence *
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msm_fence_alloc(struct msm_fence_context *fctx)
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{
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struct msm_fence *f;
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f = kzalloc(sizeof(*f), GFP_KERNEL);
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if (!f)
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return ERR_PTR(-ENOMEM);
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f->fctx = fctx;
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dma_fence_init(&f->base, &msm_fence_ops, &fctx->spinlock,
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fctx->context, ++fctx->last_fence);
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return &f->base;
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}
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