forked from Minki/linux
debe6a623d
Add coverage for OCTEON III models. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8942/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
371 lines
9.9 KiB
C
371 lines
9.9 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com>
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* Copyright (C) 2000, 2001 Ralf Baechle <ralf@gnu.org>
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* Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com>
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* swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
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* IP32 changes by Ilya.
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* Copyright (C) 2010 Cavium Networks, Inc.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/scatterlist.h>
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#include <linux/bootmem.h>
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#include <linux/export.h>
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#include <linux/swiotlb.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <asm/bootinfo.h>
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#include <asm/octeon/octeon.h>
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#ifdef CONFIG_PCI
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#include <asm/octeon/pci-octeon.h>
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#include <asm/octeon/cvmx-npi-defs.h>
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#include <asm/octeon/cvmx-pci-defs.h>
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static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr)
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{
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if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE))
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return paddr - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
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else
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return paddr;
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}
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static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr)
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{
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if (daddr >= CVMX_PCIE_BAR1_RC_BASE)
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return daddr + CVMX_PCIE_BAR1_PHYS_BASE - CVMX_PCIE_BAR1_RC_BASE;
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else
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return daddr;
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}
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static dma_addr_t octeon_gen1_phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
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paddr -= 0x400000000ull;
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return octeon_hole_phys_to_dma(paddr);
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}
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static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
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{
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daddr = octeon_hole_dma_to_phys(daddr);
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if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
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daddr += 0x400000000ull;
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return daddr;
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}
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static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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return octeon_hole_phys_to_dma(paddr);
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}
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static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr)
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{
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return octeon_hole_dma_to_phys(daddr);
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}
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static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
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paddr -= 0x400000000ull;
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/* Anything in the BAR1 hole or above goes via BAR2 */
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if (paddr >= 0xf0000000ull)
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paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
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return paddr;
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}
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static phys_addr_t octeon_big_dma_to_phys(struct device *dev, dma_addr_t daddr)
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{
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if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
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daddr -= OCTEON_BAR2_PCI_ADDRESS;
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if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
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daddr += 0x400000000ull;
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return daddr;
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}
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static dma_addr_t octeon_small_phys_to_dma(struct device *dev,
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phys_addr_t paddr)
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{
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if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
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paddr -= 0x400000000ull;
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/* Anything not in the BAR1 range goes via BAR2 */
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if (paddr >= octeon_bar1_pci_phys && paddr < octeon_bar1_pci_phys + 0x8000000ull)
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paddr = paddr - octeon_bar1_pci_phys;
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else
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paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
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return paddr;
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}
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static phys_addr_t octeon_small_dma_to_phys(struct device *dev,
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dma_addr_t daddr)
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{
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if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
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daddr -= OCTEON_BAR2_PCI_ADDRESS;
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else
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daddr += octeon_bar1_pci_phys;
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if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
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daddr += 0x400000000ull;
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return daddr;
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}
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#endif /* CONFIG_PCI */
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static dma_addr_t octeon_dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size, enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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dma_addr_t daddr = swiotlb_map_page(dev, page, offset, size,
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direction, attrs);
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mb();
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return daddr;
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}
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static int octeon_dma_map_sg(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction direction, struct dma_attrs *attrs)
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{
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int r = swiotlb_map_sg_attrs(dev, sg, nents, direction, attrs);
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mb();
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return r;
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}
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static void octeon_dma_sync_single_for_device(struct device *dev,
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dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
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{
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swiotlb_sync_single_for_device(dev, dma_handle, size, direction);
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mb();
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}
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static void octeon_dma_sync_sg_for_device(struct device *dev,
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struct scatterlist *sg, int nelems, enum dma_data_direction direction)
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{
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swiotlb_sync_sg_for_device(dev, sg, nelems, direction);
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mb();
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}
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static void *octeon_dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp, struct dma_attrs *attrs)
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{
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void *ret;
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if (dma_alloc_from_coherent(dev, size, dma_handle, &ret))
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return ret;
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/* ignore region specifiers */
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gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
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#ifdef CONFIG_ZONE_DMA
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if (dev == NULL)
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gfp |= __GFP_DMA;
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else if (dev->coherent_dma_mask <= DMA_BIT_MASK(24))
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gfp |= __GFP_DMA;
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else
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#endif
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#ifdef CONFIG_ZONE_DMA32
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if (dev->coherent_dma_mask <= DMA_BIT_MASK(32))
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gfp |= __GFP_DMA32;
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else
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#endif
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;
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/* Don't invoke OOM killer */
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gfp |= __GFP_NORETRY;
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ret = swiotlb_alloc_coherent(dev, size, dma_handle, gfp);
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mb();
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return ret;
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}
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static void octeon_dma_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle, struct dma_attrs *attrs)
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{
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int order = get_order(size);
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if (dma_release_from_coherent(dev, order, vaddr))
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return;
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swiotlb_free_coherent(dev, size, vaddr, dma_handle);
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}
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static dma_addr_t octeon_unity_phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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return paddr;
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}
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static phys_addr_t octeon_unity_dma_to_phys(struct device *dev, dma_addr_t daddr)
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{
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return daddr;
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}
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struct octeon_dma_map_ops {
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struct dma_map_ops dma_map_ops;
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dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr);
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phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
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};
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dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
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struct octeon_dma_map_ops,
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dma_map_ops);
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return ops->phys_to_dma(dev, paddr);
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}
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EXPORT_SYMBOL(phys_to_dma);
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phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
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{
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struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
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struct octeon_dma_map_ops,
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dma_map_ops);
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return ops->dma_to_phys(dev, daddr);
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}
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EXPORT_SYMBOL(dma_to_phys);
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static struct octeon_dma_map_ops octeon_linear_dma_map_ops = {
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.dma_map_ops = {
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.alloc = octeon_dma_alloc_coherent,
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.free = octeon_dma_free_coherent,
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.map_page = octeon_dma_map_page,
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.unmap_page = swiotlb_unmap_page,
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.map_sg = octeon_dma_map_sg,
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.unmap_sg = swiotlb_unmap_sg_attrs,
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.sync_single_for_cpu = swiotlb_sync_single_for_cpu,
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.sync_single_for_device = octeon_dma_sync_single_for_device,
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.sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
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.sync_sg_for_device = octeon_dma_sync_sg_for_device,
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.mapping_error = swiotlb_dma_mapping_error,
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.dma_supported = swiotlb_dma_supported
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},
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.phys_to_dma = octeon_unity_phys_to_dma,
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.dma_to_phys = octeon_unity_dma_to_phys
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};
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char *octeon_swiotlb;
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void __init plat_swiotlb_setup(void)
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{
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int i;
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phys_addr_t max_addr;
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phys_addr_t addr_size;
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size_t swiotlbsize;
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unsigned long swiotlb_nslabs;
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max_addr = 0;
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addr_size = 0;
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for (i = 0 ; i < boot_mem_map.nr_map; i++) {
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struct boot_mem_map_entry *e = &boot_mem_map.map[i];
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if (e->type != BOOT_MEM_RAM && e->type != BOOT_MEM_INIT_RAM)
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continue;
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/* These addresses map low for PCI. */
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if (e->addr > 0x410000000ull && !OCTEON_IS_OCTEON2())
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continue;
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addr_size += e->size;
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if (max_addr < e->addr + e->size)
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max_addr = e->addr + e->size;
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}
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swiotlbsize = PAGE_SIZE;
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#ifdef CONFIG_PCI
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/*
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* For OCTEON_DMA_BAR_TYPE_SMALL, size the iotlb at 1/4 memory
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* size to a maximum of 64MB
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*/
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if (OCTEON_IS_MODEL(OCTEON_CN31XX)
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|| OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
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swiotlbsize = addr_size / 4;
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if (swiotlbsize > 64 * (1<<20))
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swiotlbsize = 64 * (1<<20);
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} else if (max_addr > 0xf0000000ul) {
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/*
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* Otherwise only allocate a big iotlb if there is
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* memory past the BAR1 hole.
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*/
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swiotlbsize = 64 * (1<<20);
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}
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#endif
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#ifdef CONFIG_USB_OCTEON_OHCI
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/* OCTEON II ohci is only 32-bit. */
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if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul)
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swiotlbsize = 64 * (1<<20);
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#endif
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swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
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swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
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swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT;
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octeon_swiotlb = alloc_bootmem_low_pages(swiotlbsize);
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if (swiotlb_init_with_tbl(octeon_swiotlb, swiotlb_nslabs, 1) == -ENOMEM)
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panic("Cannot allocate SWIOTLB buffer");
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mips_dma_map_ops = &octeon_linear_dma_map_ops.dma_map_ops;
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}
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#ifdef CONFIG_PCI
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static struct octeon_dma_map_ops _octeon_pci_dma_map_ops = {
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.dma_map_ops = {
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.alloc = octeon_dma_alloc_coherent,
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.free = octeon_dma_free_coherent,
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.map_page = octeon_dma_map_page,
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.unmap_page = swiotlb_unmap_page,
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.map_sg = octeon_dma_map_sg,
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.unmap_sg = swiotlb_unmap_sg_attrs,
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.sync_single_for_cpu = swiotlb_sync_single_for_cpu,
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.sync_single_for_device = octeon_dma_sync_single_for_device,
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.sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
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.sync_sg_for_device = octeon_dma_sync_sg_for_device,
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.mapping_error = swiotlb_dma_mapping_error,
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.dma_supported = swiotlb_dma_supported
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},
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};
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struct dma_map_ops *octeon_pci_dma_map_ops;
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void __init octeon_pci_dma_init(void)
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{
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switch (octeon_dma_bar_type) {
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case OCTEON_DMA_BAR_TYPE_PCIE2:
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_octeon_pci_dma_map_ops.phys_to_dma = octeon_gen2_phys_to_dma;
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_octeon_pci_dma_map_ops.dma_to_phys = octeon_gen2_dma_to_phys;
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break;
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case OCTEON_DMA_BAR_TYPE_PCIE:
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_octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma;
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_octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys;
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break;
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case OCTEON_DMA_BAR_TYPE_BIG:
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_octeon_pci_dma_map_ops.phys_to_dma = octeon_big_phys_to_dma;
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_octeon_pci_dma_map_ops.dma_to_phys = octeon_big_dma_to_phys;
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break;
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case OCTEON_DMA_BAR_TYPE_SMALL:
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_octeon_pci_dma_map_ops.phys_to_dma = octeon_small_phys_to_dma;
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_octeon_pci_dma_map_ops.dma_to_phys = octeon_small_dma_to_phys;
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break;
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default:
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BUG();
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}
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octeon_pci_dma_map_ops = &_octeon_pci_dma_map_ops.dma_map_ops;
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}
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#endif /* CONFIG_PCI */
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