49acadff2a
Now when we switched to usage of real clk devices for CPU core frequency those root properties make no sense any longer. Se we're just getting rid of them here to not confuse readers of our .dts files. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Christian Ruppert <christian.ruppert@alitech.com> Cc: Noam Camus <noamca@mellanox.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
84 lines
1.8 KiB
Plaintext
84 lines
1.8 KiB
Plaintext
/*
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* Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* Device tree for AXC003 CPU card:
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* HS38x2 (Dual Core) with IDU intc (VDK version)
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*/
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/include/ "skeleton_hs_idu.dtsi"
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/ {
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compatible = "snps,arc";
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#address-cells = <1>;
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#size-cells = <1>;
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cpu_card {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0xf0000000 0x10000000>;
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core_clk: core_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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core_intc: archs-intc@cpu {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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interrupt-parent = <&core_intc>;
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/*
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* <hwirq distribution>
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* distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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*/
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#interrupt-cells = <2>;
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interrupts = <24 25 26 27>;
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};
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debug_uart: dw-apb-uart@0x5000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x5000 0x100>;
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clock-frequency = <2403200>;
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interrupt-parent = <&idu_intc>;
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interrupts = <2 0>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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};
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mb_intc: dw-apb-ictl@0xe0012000 {
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#interrupt-cells = <1>;
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compatible = "snps,dw-apb-ictl";
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reg = < 0xe0012000 0x200 >;
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interrupt-controller;
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interrupt-parent = <&idu_intc>;
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interrupts = < 0 0 >;
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};
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memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x80000000 0x40000000>;
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device_type = "memory";
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reg = <0x80000000 0x20000000>; /* 512MiB */
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};
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};
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