forked from Minki/linux
d8f60cfc93
This enables the use of interrupts on r6xx/r7xx hardware.
Interrupts are implemented via a ring buffer. The GPU adds
interrupts vectors to the ring and the host reads them off
in the interrupt handler. The interrupt controller requires
firmware like the CP. This firmware must be installed and
accessble to the firmware loader for interrupts to function.
MSIs don't seem to work on my RS780. They work fine on all
my discrete cards. I'm not sure about other RS780s or
RS880s. I've disabled MSIs on RS780 and RS880, but it would
probably be worth checking on some other systems.
v2 - fix some checkpatch.pl problems;
re-read the disp int status reg if we restart the ih;
v3 - remove the irq handler if r600_irq_init() fails;
remove spinlock in r600_ih_ring_fini();
move ih rb overflow check to r600_get_ih_wptr();
move irq ack to separate function;
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
389 lines
10 KiB
C
389 lines
10 KiB
C
/*
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* Copyright 2009 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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* Dave Airlie
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*/
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#include <linux/seq_file.h>
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#include <asm/atomic.h>
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#include <linux/wait.h>
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#include <linux/list.h>
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#include <linux/kref.h>
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#include "drmP.h"
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#include "drm.h"
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#include "radeon_reg.h"
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#include "radeon.h"
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int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
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{
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unsigned long irq_flags;
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write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
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if (fence->emited) {
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write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
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return 0;
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}
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fence->seq = atomic_add_return(1, &rdev->fence_drv.seq);
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if (!rdev->cp.ready) {
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/* FIXME: cp is not running assume everythings is done right
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* away
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*/
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WREG32(rdev->fence_drv.scratch_reg, fence->seq);
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} else
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radeon_fence_ring_emit(rdev, fence);
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fence->emited = true;
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fence->timeout = jiffies + ((2000 * HZ) / 1000);
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list_del(&fence->list);
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list_add_tail(&fence->list, &rdev->fence_drv.emited);
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write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
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return 0;
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}
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static bool radeon_fence_poll_locked(struct radeon_device *rdev)
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{
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struct radeon_fence *fence;
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struct list_head *i, *n;
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uint32_t seq;
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bool wake = false;
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if (rdev == NULL) {
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return true;
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}
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if (rdev->shutdown) {
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return true;
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}
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seq = RREG32(rdev->fence_drv.scratch_reg);
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rdev->fence_drv.last_seq = seq;
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n = NULL;
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list_for_each(i, &rdev->fence_drv.emited) {
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fence = list_entry(i, struct radeon_fence, list);
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if (fence->seq == seq) {
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n = i;
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break;
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}
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}
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/* all fence previous to this one are considered as signaled */
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if (n) {
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i = n;
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do {
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n = i->prev;
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list_del(i);
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list_add_tail(i, &rdev->fence_drv.signaled);
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fence = list_entry(i, struct radeon_fence, list);
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fence->signaled = true;
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i = n;
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} while (i != &rdev->fence_drv.emited);
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wake = true;
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}
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return wake;
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}
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static void radeon_fence_destroy(struct kref *kref)
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{
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unsigned long irq_flags;
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struct radeon_fence *fence;
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fence = container_of(kref, struct radeon_fence, kref);
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write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
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list_del(&fence->list);
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fence->emited = false;
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write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
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kfree(fence);
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}
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int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence)
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{
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unsigned long irq_flags;
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*fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
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if ((*fence) == NULL) {
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return -ENOMEM;
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}
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kref_init(&((*fence)->kref));
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(*fence)->rdev = rdev;
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(*fence)->emited = false;
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(*fence)->signaled = false;
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(*fence)->seq = 0;
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INIT_LIST_HEAD(&(*fence)->list);
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write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
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list_add_tail(&(*fence)->list, &rdev->fence_drv.created);
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write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
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return 0;
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}
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bool radeon_fence_signaled(struct radeon_fence *fence)
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{
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struct radeon_device *rdev = fence->rdev;
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unsigned long irq_flags;
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bool signaled = false;
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if (rdev->gpu_lockup) {
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return true;
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}
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if (fence == NULL) {
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return true;
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}
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write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
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signaled = fence->signaled;
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/* if we are shuting down report all fence as signaled */
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if (fence->rdev->shutdown) {
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signaled = true;
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}
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if (!fence->emited) {
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WARN(1, "Querying an unemited fence : %p !\n", fence);
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signaled = true;
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}
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if (!signaled) {
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radeon_fence_poll_locked(fence->rdev);
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signaled = fence->signaled;
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}
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write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
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return signaled;
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}
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int radeon_fence_wait(struct radeon_fence *fence, bool intr)
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{
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struct radeon_device *rdev;
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unsigned long cur_jiffies;
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unsigned long timeout;
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bool expired = false;
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int r;
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if (fence == NULL) {
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WARN(1, "Querying an invalid fence : %p !\n", fence);
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return 0;
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}
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rdev = fence->rdev;
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if (radeon_fence_signaled(fence)) {
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return 0;
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}
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retry:
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cur_jiffies = jiffies;
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timeout = HZ / 100;
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if (time_after(fence->timeout, cur_jiffies)) {
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timeout = fence->timeout - cur_jiffies;
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}
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if (intr) {
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r = wait_event_interruptible_timeout(rdev->fence_drv.queue,
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radeon_fence_signaled(fence), timeout);
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if (unlikely(r == -ERESTARTSYS)) {
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return -EBUSY;
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}
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} else {
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r = wait_event_timeout(rdev->fence_drv.queue,
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radeon_fence_signaled(fence), timeout);
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}
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if (unlikely(!radeon_fence_signaled(fence))) {
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if (unlikely(r == 0)) {
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expired = true;
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}
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if (unlikely(expired)) {
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timeout = 1;
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if (time_after(cur_jiffies, fence->timeout)) {
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timeout = cur_jiffies - fence->timeout;
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}
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timeout = jiffies_to_msecs(timeout);
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if (timeout > 500) {
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DRM_ERROR("fence(%p:0x%08X) %lums timeout "
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"going to reset GPU\n",
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fence, fence->seq, timeout);
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radeon_gpu_reset(rdev);
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WREG32(rdev->fence_drv.scratch_reg, fence->seq);
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}
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}
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goto retry;
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}
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if (unlikely(expired)) {
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rdev->fence_drv.count_timeout++;
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cur_jiffies = jiffies;
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timeout = 1;
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if (time_after(cur_jiffies, fence->timeout)) {
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timeout = cur_jiffies - fence->timeout;
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}
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timeout = jiffies_to_msecs(timeout);
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DRM_ERROR("fence(%p:0x%08X) %lums timeout\n",
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fence, fence->seq, timeout);
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DRM_ERROR("last signaled fence(0x%08X)\n",
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rdev->fence_drv.last_seq);
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}
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return 0;
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}
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int radeon_fence_wait_next(struct radeon_device *rdev)
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{
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unsigned long irq_flags;
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struct radeon_fence *fence;
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int r;
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if (rdev->gpu_lockup) {
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return 0;
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}
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write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
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if (list_empty(&rdev->fence_drv.emited)) {
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write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
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return 0;
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}
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fence = list_entry(rdev->fence_drv.emited.next,
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struct radeon_fence, list);
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radeon_fence_ref(fence);
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write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
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r = radeon_fence_wait(fence, false);
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radeon_fence_unref(&fence);
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return r;
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}
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int radeon_fence_wait_last(struct radeon_device *rdev)
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{
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unsigned long irq_flags;
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struct radeon_fence *fence;
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int r;
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if (rdev->gpu_lockup) {
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return 0;
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}
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write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
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if (list_empty(&rdev->fence_drv.emited)) {
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write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
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return 0;
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}
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fence = list_entry(rdev->fence_drv.emited.prev,
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struct radeon_fence, list);
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radeon_fence_ref(fence);
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write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
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r = radeon_fence_wait(fence, false);
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radeon_fence_unref(&fence);
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return r;
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}
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struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
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{
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kref_get(&fence->kref);
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return fence;
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}
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void radeon_fence_unref(struct radeon_fence **fence)
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{
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struct radeon_fence *tmp = *fence;
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*fence = NULL;
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if (tmp) {
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kref_put(&tmp->kref, &radeon_fence_destroy);
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}
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}
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void radeon_fence_process(struct radeon_device *rdev)
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{
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unsigned long irq_flags;
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bool wake;
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write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
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wake = radeon_fence_poll_locked(rdev);
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write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
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if (wake) {
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wake_up_all(&rdev->fence_drv.queue);
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}
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}
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int radeon_fence_driver_init(struct radeon_device *rdev)
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{
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unsigned long irq_flags;
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int r;
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write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
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r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
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if (r) {
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DRM_ERROR("Fence failed to get a scratch register.");
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write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
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return r;
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}
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WREG32(rdev->fence_drv.scratch_reg, 0);
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atomic_set(&rdev->fence_drv.seq, 0);
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INIT_LIST_HEAD(&rdev->fence_drv.created);
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INIT_LIST_HEAD(&rdev->fence_drv.emited);
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INIT_LIST_HEAD(&rdev->fence_drv.signaled);
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rdev->fence_drv.count_timeout = 0;
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init_waitqueue_head(&rdev->fence_drv.queue);
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write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
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if (radeon_debugfs_fence_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for fence !\n");
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}
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return 0;
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}
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void radeon_fence_driver_fini(struct radeon_device *rdev)
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{
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unsigned long irq_flags;
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wake_up_all(&rdev->fence_drv.queue);
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write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
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radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg);
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write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
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DRM_INFO("radeon: fence finalized\n");
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}
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/*
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* Fence debugfs
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*/
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#if defined(CONFIG_DEBUG_FS)
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static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *)m->private;
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struct drm_device *dev = node->minor->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_fence *fence;
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seq_printf(m, "Last signaled fence 0x%08X\n",
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RREG32(rdev->fence_drv.scratch_reg));
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if (!list_empty(&rdev->fence_drv.emited)) {
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fence = list_entry(rdev->fence_drv.emited.prev,
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struct radeon_fence, list);
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seq_printf(m, "Last emited fence %p with 0x%08X\n",
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fence, fence->seq);
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}
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return 0;
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}
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static struct drm_info_list radeon_debugfs_fence_list[] = {
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{"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
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};
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#endif
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int radeon_debugfs_fence_init(struct radeon_device *rdev)
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{
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#if defined(CONFIG_DEBUG_FS)
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return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
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#else
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return 0;
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#endif
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}
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