Upper level runtime need the xgmi hops info to determine the data path Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
		
			
				
	
	
		
			328 lines
		
	
	
		
			8.9 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			328 lines
		
	
	
		
			8.9 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright 2014 Advanced Micro Devices, Inc.
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|  *
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|  * Permission is hereby granted, free of charge, to any person obtaining a
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|  * copy of this software and associated documentation files (the "Software"),
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|  * to deal in the Software without restriction, including without limitation
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|  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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|  * and/or sell copies of the Software, and to permit persons to whom the
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|  * Software is furnished to do so, subject to the following conditions:
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|  *
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|  * The above copyright notice and this permission notice shall be included in
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|  * all copies or substantial portions of the Software.
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|  *
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|  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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|  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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|  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
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|  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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|  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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|  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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|  * OTHER DEALINGS IN THE SOFTWARE.
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|  */
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| 
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| #ifndef KFD_CRAT_H_INCLUDED
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| #define KFD_CRAT_H_INCLUDED
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| 
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| #include <linux/types.h>
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| 
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| #pragma pack(1)
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| 
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| /*
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|  * 4CC signature values for the CRAT and CDIT ACPI tables
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|  */
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| 
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| #define CRAT_SIGNATURE	"CRAT"
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| #define CDIT_SIGNATURE	"CDIT"
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| 
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| /*
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|  * Component Resource Association Table (CRAT)
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|  */
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| 
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| #define CRAT_OEMID_LENGTH	6
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| #define CRAT_OEMTABLEID_LENGTH	8
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| #define CRAT_RESERVED_LENGTH	6
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| 
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| #define CRAT_OEMID_64BIT_MASK ((1ULL << (CRAT_OEMID_LENGTH * 8)) - 1)
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| 
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| /* Compute Unit flags */
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| #define COMPUTE_UNIT_CPU	(1 << 0)  /* Create Virtual CRAT for CPU */
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| #define COMPUTE_UNIT_GPU	(1 << 1)  /* Create Virtual CRAT for GPU */
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| 
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| struct crat_header {
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| 	uint32_t	signature;
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| 	uint32_t	length;
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| 	uint8_t		revision;
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| 	uint8_t		checksum;
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| 	uint8_t		oem_id[CRAT_OEMID_LENGTH];
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| 	uint8_t		oem_table_id[CRAT_OEMTABLEID_LENGTH];
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| 	uint32_t	oem_revision;
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| 	uint32_t	creator_id;
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| 	uint32_t	creator_revision;
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| 	uint32_t	total_entries;
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| 	uint16_t	num_domains;
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| 	uint8_t		reserved[CRAT_RESERVED_LENGTH];
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| };
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| 
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| /*
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|  * The header structure is immediately followed by total_entries of the
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|  * data definitions
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|  */
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| 
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| /*
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|  * The currently defined subtype entries in the CRAT
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|  */
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| #define CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY	0
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| #define CRAT_SUBTYPE_MEMORY_AFFINITY		1
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| #define CRAT_SUBTYPE_CACHE_AFFINITY		2
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| #define CRAT_SUBTYPE_TLB_AFFINITY		3
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| #define CRAT_SUBTYPE_CCOMPUTE_AFFINITY		4
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| #define CRAT_SUBTYPE_IOLINK_AFFINITY		5
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| #define CRAT_SUBTYPE_MAX			6
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| 
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| #define CRAT_SIBLINGMAP_SIZE	32
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| 
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| /*
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|  * ComputeUnit Affinity structure and definitions
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|  */
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| #define CRAT_CU_FLAGS_ENABLED		0x00000001
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| #define CRAT_CU_FLAGS_HOT_PLUGGABLE	0x00000002
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| #define CRAT_CU_FLAGS_CPU_PRESENT	0x00000004
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| #define CRAT_CU_FLAGS_GPU_PRESENT	0x00000008
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| #define CRAT_CU_FLAGS_IOMMU_PRESENT	0x00000010
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| #define CRAT_CU_FLAGS_RESERVED		0xffffffe0
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| 
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| #define CRAT_COMPUTEUNIT_RESERVED_LENGTH 4
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| 
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| struct crat_subtype_computeunit {
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| 	uint8_t		type;
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| 	uint8_t		length;
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| 	uint16_t	reserved;
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| 	uint32_t	flags;
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| 	uint32_t	proximity_domain;
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| 	uint32_t	processor_id_low;
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| 	uint16_t	num_cpu_cores;
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| 	uint16_t	num_simd_cores;
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| 	uint16_t	max_waves_simd;
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| 	uint16_t	io_count;
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| 	uint16_t	hsa_capability;
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| 	uint16_t	lds_size_in_kb;
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| 	uint8_t		wave_front_size;
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| 	uint8_t		num_banks;
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| 	uint16_t	micro_engine_id;
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| 	uint8_t		array_count;
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| 	uint8_t		num_cu_per_array;
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| 	uint8_t		num_simd_per_cu;
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| 	uint8_t		max_slots_scatch_cu;
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| 	uint8_t		reserved2[CRAT_COMPUTEUNIT_RESERVED_LENGTH];
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| };
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| 
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| /*
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|  * HSA Memory Affinity structure and definitions
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|  */
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| #define CRAT_MEM_FLAGS_ENABLED		0x00000001
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| #define CRAT_MEM_FLAGS_HOT_PLUGGABLE	0x00000002
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| #define CRAT_MEM_FLAGS_NON_VOLATILE	0x00000004
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| #define CRAT_MEM_FLAGS_RESERVED		0xfffffff8
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| 
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| #define CRAT_MEMORY_RESERVED_LENGTH 8
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| 
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| struct crat_subtype_memory {
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| 	uint8_t		type;
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| 	uint8_t		length;
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| 	uint16_t	reserved;
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| 	uint32_t	flags;
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| 	uint32_t	proximity_domain;
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| 	uint32_t	base_addr_low;
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| 	uint32_t	base_addr_high;
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| 	uint32_t	length_low;
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| 	uint32_t	length_high;
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| 	uint32_t	width;
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| 	uint8_t		visibility_type; /* for virtual (dGPU) CRAT */
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| 	uint8_t		reserved2[CRAT_MEMORY_RESERVED_LENGTH - 1];
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| };
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| 
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| /*
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|  * HSA Cache Affinity structure and definitions
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|  */
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| #define CRAT_CACHE_FLAGS_ENABLED	0x00000001
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| #define CRAT_CACHE_FLAGS_DATA_CACHE	0x00000002
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| #define CRAT_CACHE_FLAGS_INST_CACHE	0x00000004
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| #define CRAT_CACHE_FLAGS_CPU_CACHE	0x00000008
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| #define CRAT_CACHE_FLAGS_SIMD_CACHE	0x00000010
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| #define CRAT_CACHE_FLAGS_RESERVED	0xffffffe0
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| 
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| #define CRAT_CACHE_RESERVED_LENGTH 8
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| 
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| struct crat_subtype_cache {
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| 	uint8_t		type;
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| 	uint8_t		length;
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| 	uint16_t	reserved;
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| 	uint32_t	flags;
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| 	uint32_t	processor_id_low;
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| 	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
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| 	uint32_t	cache_size;
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| 	uint8_t		cache_level;
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| 	uint8_t		lines_per_tag;
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| 	uint16_t	cache_line_size;
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| 	uint8_t		associativity;
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| 	uint8_t		cache_properties;
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| 	uint16_t	cache_latency;
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| 	uint8_t		reserved2[CRAT_CACHE_RESERVED_LENGTH];
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| };
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| 
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| /*
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|  * HSA TLB Affinity structure and definitions
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|  */
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| #define CRAT_TLB_FLAGS_ENABLED	0x00000001
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| #define CRAT_TLB_FLAGS_DATA_TLB	0x00000002
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| #define CRAT_TLB_FLAGS_INST_TLB	0x00000004
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| #define CRAT_TLB_FLAGS_CPU_TLB	0x00000008
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| #define CRAT_TLB_FLAGS_SIMD_TLB	0x00000010
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| #define CRAT_TLB_FLAGS_RESERVED	0xffffffe0
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| 
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| #define CRAT_TLB_RESERVED_LENGTH 4
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| 
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| struct crat_subtype_tlb {
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| 	uint8_t		type;
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| 	uint8_t		length;
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| 	uint16_t	reserved;
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| 	uint32_t	flags;
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| 	uint32_t	processor_id_low;
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| 	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
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| 	uint32_t	tlb_level;
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| 	uint8_t		data_tlb_associativity_2mb;
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| 	uint8_t		data_tlb_size_2mb;
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| 	uint8_t		instruction_tlb_associativity_2mb;
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| 	uint8_t		instruction_tlb_size_2mb;
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| 	uint8_t		data_tlb_associativity_4k;
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| 	uint8_t		data_tlb_size_4k;
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| 	uint8_t		instruction_tlb_associativity_4k;
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| 	uint8_t		instruction_tlb_size_4k;
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| 	uint8_t		data_tlb_associativity_1gb;
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| 	uint8_t		data_tlb_size_1gb;
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| 	uint8_t		instruction_tlb_associativity_1gb;
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| 	uint8_t		instruction_tlb_size_1gb;
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| 	uint8_t		reserved2[CRAT_TLB_RESERVED_LENGTH];
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| };
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| 
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| /*
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|  * HSA CCompute/APU Affinity structure and definitions
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|  */
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| #define CRAT_CCOMPUTE_FLAGS_ENABLED	0x00000001
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| #define CRAT_CCOMPUTE_FLAGS_RESERVED	0xfffffffe
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| 
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| #define CRAT_CCOMPUTE_RESERVED_LENGTH 16
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| 
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| struct crat_subtype_ccompute {
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| 	uint8_t		type;
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| 	uint8_t		length;
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| 	uint16_t	reserved;
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| 	uint32_t	flags;
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| 	uint32_t	processor_id_low;
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| 	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
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| 	uint32_t	apu_size;
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| 	uint8_t		reserved2[CRAT_CCOMPUTE_RESERVED_LENGTH];
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| };
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| 
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| /*
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|  * HSA IO Link Affinity structure and definitions
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|  */
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| #define CRAT_IOLINK_FLAGS_ENABLED		(1 << 0)
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| #define CRAT_IOLINK_FLAGS_NON_COHERENT		(1 << 1)
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| #define CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT	(1 << 2)
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| #define CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT	(1 << 3)
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| #define CRAT_IOLINK_FLAGS_NO_PEER_TO_PEER_DMA	(1 << 4)
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| #define CRAT_IOLINK_FLAGS_BI_DIRECTIONAL 	(1 << 31)
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| #define CRAT_IOLINK_FLAGS_RESERVED_MASK		0x7fffffe0
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| 
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| /*
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|  * IO interface types
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|  */
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| #define CRAT_IOLINK_TYPE_UNDEFINED	0
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| #define CRAT_IOLINK_TYPE_HYPERTRANSPORT	1
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| #define CRAT_IOLINK_TYPE_PCIEXPRESS	2
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| #define CRAT_IOLINK_TYPE_AMBA		3
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| #define CRAT_IOLINK_TYPE_MIPI		4
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| #define CRAT_IOLINK_TYPE_QPI_1_1	5
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| #define CRAT_IOLINK_TYPE_RESERVED1	6
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| #define CRAT_IOLINK_TYPE_RESERVED2	7
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| #define CRAT_IOLINK_TYPE_RAPID_IO	8
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| #define CRAT_IOLINK_TYPE_INFINIBAND	9
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| #define CRAT_IOLINK_TYPE_RESERVED3	10
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| #define CRAT_IOLINK_TYPE_XGMI		11
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| #define CRAT_IOLINK_TYPE_XGOP		12
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| #define CRAT_IOLINK_TYPE_GZ		13
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| #define CRAT_IOLINK_TYPE_ETHERNET_RDMA	14
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| #define CRAT_IOLINK_TYPE_RDMA_OTHER	15
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| #define CRAT_IOLINK_TYPE_OTHER		16
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| #define CRAT_IOLINK_TYPE_MAX		255
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| 
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| #define CRAT_IOLINK_RESERVED_LENGTH	24
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| 
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| struct crat_subtype_iolink {
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| 	uint8_t		type;
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| 	uint8_t		length;
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| 	uint16_t	reserved;
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| 	uint32_t	flags;
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| 	uint32_t	proximity_domain_from;
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| 	uint32_t	proximity_domain_to;
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| 	uint8_t		io_interface_type;
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| 	uint8_t		version_major;
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| 	uint16_t	version_minor;
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| 	uint32_t	minimum_latency;
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| 	uint32_t	maximum_latency;
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| 	uint32_t	minimum_bandwidth_mbs;
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| 	uint32_t	maximum_bandwidth_mbs;
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| 	uint32_t	recommended_transfer_size;
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| 	uint8_t		reserved2[CRAT_IOLINK_RESERVED_LENGTH - 1];
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| 	uint8_t		num_hops_xgmi;
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| };
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| 
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| /*
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|  * HSA generic sub-type header
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|  */
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| 
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| #define CRAT_SUBTYPE_FLAGS_ENABLED 0x00000001
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| 
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| struct crat_subtype_generic {
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| 	uint8_t		type;
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| 	uint8_t		length;
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| 	uint16_t	reserved;
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| 	uint32_t	flags;
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| };
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| 
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| /*
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|  * Component Locality Distance Information Table (CDIT)
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|  */
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| #define CDIT_OEMID_LENGTH	6
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| #define CDIT_OEMTABLEID_LENGTH	8
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| 
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| struct cdit_header {
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| 	uint32_t	signature;
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| 	uint32_t	length;
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| 	uint8_t		revision;
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| 	uint8_t		checksum;
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| 	uint8_t		oem_id[CDIT_OEMID_LENGTH];
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| 	uint8_t		oem_table_id[CDIT_OEMTABLEID_LENGTH];
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| 	uint32_t	oem_revision;
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| 	uint32_t	creator_id;
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| 	uint32_t	creator_revision;
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| 	uint32_t	total_entries;
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| 	uint16_t	num_domains;
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| 	uint8_t		entry[1];
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| };
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| 
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| #pragma pack()
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| 
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| struct kfd_dev;
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| 
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| int kfd_create_crat_image_acpi(void **crat_image, size_t *size);
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| void kfd_destroy_crat_image(void *crat_image);
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| int kfd_parse_crat_table(void *crat_image, struct list_head *device_list,
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| 			 uint32_t proximity_domain);
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| int kfd_create_crat_image_virtual(void **crat_image, size_t *size,
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| 				  int flags, struct kfd_dev *kdev,
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| 				  uint32_t proximity_domain);
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| 
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| #endif /* KFD_CRAT_H_INCLUDED */
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