forked from Minki/linux
d748c9810b
Armada38x wants to modify its rtc_class_ops to remove the interrupt handling when there is no usable interrupt, but this means we leave function pointers in writable memory. Since rtc_class_ops is small, arrange to have two instances, one for when we have interrupts, and one for when we have none, both marked const. This allows the compiler to place them in read-only memory, which is better than placing them in __ro_after_init. Thanks to Bhumika Goyal <bhumirks@gmail.com> for pointing out that the structure was writable and submitting a patch to add __ro_after_init. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
395 lines
9.5 KiB
C
395 lines
9.5 KiB
C
/*
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* RTC driver for the Armada 38x Marvell SoCs
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*
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* Copyright (C) 2015 Marvell
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*
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* Gregory Clement <gregory.clement@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/rtc.h>
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#define RTC_STATUS 0x0
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#define RTC_STATUS_ALARM1 BIT(0)
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#define RTC_STATUS_ALARM2 BIT(1)
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#define RTC_IRQ1_CONF 0x4
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#define RTC_IRQ1_AL_EN BIT(0)
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#define RTC_IRQ1_FREQ_EN BIT(1)
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#define RTC_IRQ1_FREQ_1HZ BIT(2)
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#define RTC_TIME 0xC
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#define RTC_ALARM1 0x10
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#define SOC_RTC_BRIDGE_TIMING_CTL 0x0
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#define SOC_RTC_PERIOD_OFFS 0
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#define SOC_RTC_PERIOD_MASK (0x3FF << SOC_RTC_PERIOD_OFFS)
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#define SOC_RTC_READ_DELAY_OFFS 26
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#define SOC_RTC_READ_DELAY_MASK (0x1F << SOC_RTC_READ_DELAY_OFFS)
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#define SOC_RTC_INTERRUPT 0x8
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#define SOC_RTC_ALARM1 BIT(0)
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#define SOC_RTC_ALARM2 BIT(1)
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#define SOC_RTC_ALARM1_MASK BIT(2)
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#define SOC_RTC_ALARM2_MASK BIT(3)
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#define SAMPLE_NR 100
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struct value_to_freq {
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u32 value;
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u8 freq;
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};
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struct armada38x_rtc {
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struct rtc_device *rtc_dev;
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void __iomem *regs;
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void __iomem *regs_soc;
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spinlock_t lock;
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int irq;
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struct value_to_freq *val_to_freq;
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};
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/*
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* According to the datasheet, the OS should wait 5us after every
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* register write to the RTC hard macro so that the required update
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* can occur without holding off the system bus
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* According to errata RES-3124064, Write to any RTC register
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* may fail. As a workaround, before writing to RTC
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* register, issue a dummy write of 0x0 twice to RTC Status
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* register.
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*/
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static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset)
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{
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writel(0, rtc->regs + RTC_STATUS);
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writel(0, rtc->regs + RTC_STATUS);
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writel(val, rtc->regs + offset);
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udelay(5);
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}
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/* Update RTC-MBUS bridge timing parameters */
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static void rtc_update_mbus_timing_params(struct armada38x_rtc *rtc)
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{
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u32 reg;
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reg = readl(rtc->regs_soc + SOC_RTC_BRIDGE_TIMING_CTL);
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reg &= ~SOC_RTC_PERIOD_MASK;
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reg |= 0x3FF << SOC_RTC_PERIOD_OFFS; /* Maximum value */
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reg &= ~SOC_RTC_READ_DELAY_MASK;
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reg |= 0x1F << SOC_RTC_READ_DELAY_OFFS; /* Maximum value */
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writel(reg, rtc->regs_soc + SOC_RTC_BRIDGE_TIMING_CTL);
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}
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static u32 read_rtc_register_wa(struct armada38x_rtc *rtc, u8 rtc_reg)
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{
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int i, index_max = 0, max = 0;
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for (i = 0; i < SAMPLE_NR; i++) {
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rtc->val_to_freq[i].value = readl(rtc->regs + rtc_reg);
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rtc->val_to_freq[i].freq = 0;
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}
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for (i = 0; i < SAMPLE_NR; i++) {
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int j = 0;
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u32 value = rtc->val_to_freq[i].value;
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while (rtc->val_to_freq[j].freq) {
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if (rtc->val_to_freq[j].value == value) {
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rtc->val_to_freq[j].freq++;
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break;
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}
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j++;
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}
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if (!rtc->val_to_freq[j].freq) {
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rtc->val_to_freq[j].value = value;
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rtc->val_to_freq[j].freq = 1;
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}
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if (rtc->val_to_freq[j].freq > max) {
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index_max = j;
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max = rtc->val_to_freq[j].freq;
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}
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/*
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* If a value already has half of the sample this is the most
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* frequent one and we can stop the research right now
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*/
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if (max > SAMPLE_NR / 2)
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break;
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}
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return rtc->val_to_freq[index_max].value;
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}
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static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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unsigned long time, flags;
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spin_lock_irqsave(&rtc->lock, flags);
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time = read_rtc_register_wa(rtc, RTC_TIME);
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spin_unlock_irqrestore(&rtc->lock, flags);
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rtc_time_to_tm(time, tm);
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return 0;
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}
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static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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int ret = 0;
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unsigned long time, flags;
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ret = rtc_tm_to_time(tm, &time);
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if (ret)
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goto out;
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spin_lock_irqsave(&rtc->lock, flags);
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rtc_delayed_write(time, rtc, RTC_TIME);
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spin_unlock_irqrestore(&rtc->lock, flags);
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out:
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return ret;
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}
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static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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unsigned long time, flags;
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u32 val;
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spin_lock_irqsave(&rtc->lock, flags);
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time = read_rtc_register_wa(rtc, RTC_ALARM1);
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val = read_rtc_register_wa(rtc, RTC_IRQ1_CONF) & RTC_IRQ1_AL_EN;
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spin_unlock_irqrestore(&rtc->lock, flags);
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alrm->enabled = val ? 1 : 0;
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rtc_time_to_tm(time, &alrm->time);
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return 0;
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}
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static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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unsigned long time, flags;
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int ret = 0;
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u32 val;
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ret = rtc_tm_to_time(&alrm->time, &time);
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if (ret)
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goto out;
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spin_lock_irqsave(&rtc->lock, flags);
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rtc_delayed_write(time, rtc, RTC_ALARM1);
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if (alrm->enabled) {
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rtc_delayed_write(RTC_IRQ1_AL_EN, rtc, RTC_IRQ1_CONF);
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val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
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writel(val | SOC_RTC_ALARM1_MASK,
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rtc->regs_soc + SOC_RTC_INTERRUPT);
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}
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spin_unlock_irqrestore(&rtc->lock, flags);
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out:
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return ret;
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}
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static int armada38x_rtc_alarm_irq_enable(struct device *dev,
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unsigned int enabled)
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{
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struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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unsigned long flags;
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spin_lock_irqsave(&rtc->lock, flags);
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if (enabled)
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rtc_delayed_write(RTC_IRQ1_AL_EN, rtc, RTC_IRQ1_CONF);
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else
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rtc_delayed_write(0, rtc, RTC_IRQ1_CONF);
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spin_unlock_irqrestore(&rtc->lock, flags);
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return 0;
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}
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static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data)
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{
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struct armada38x_rtc *rtc = data;
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u32 val;
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int event = RTC_IRQF | RTC_AF;
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dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq);
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spin_lock(&rtc->lock);
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val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
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writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT);
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val = read_rtc_register_wa(rtc, RTC_IRQ1_CONF);
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/* disable all the interrupts for alarm 1 */
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rtc_delayed_write(0, rtc, RTC_IRQ1_CONF);
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/* Ack the event */
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rtc_delayed_write(RTC_STATUS_ALARM1, rtc, RTC_STATUS);
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spin_unlock(&rtc->lock);
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if (val & RTC_IRQ1_FREQ_EN) {
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if (val & RTC_IRQ1_FREQ_1HZ)
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event |= RTC_UF;
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else
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event |= RTC_PF;
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}
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rtc_update_irq(rtc->rtc_dev, 1, event);
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return IRQ_HANDLED;
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}
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static const struct rtc_class_ops armada38x_rtc_ops = {
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.read_time = armada38x_rtc_read_time,
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.set_time = armada38x_rtc_set_time,
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.read_alarm = armada38x_rtc_read_alarm,
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.set_alarm = armada38x_rtc_set_alarm,
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.alarm_irq_enable = armada38x_rtc_alarm_irq_enable,
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};
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static const struct rtc_class_ops armada38x_rtc_ops_noirq = {
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.read_time = armada38x_rtc_read_time,
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.set_time = armada38x_rtc_set_time,
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.read_alarm = armada38x_rtc_read_alarm,
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};
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static __init int armada38x_rtc_probe(struct platform_device *pdev)
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{
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const struct rtc_class_ops *ops;
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struct resource *res;
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struct armada38x_rtc *rtc;
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int ret;
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rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc),
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GFP_KERNEL);
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if (!rtc)
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return -ENOMEM;
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rtc->val_to_freq = devm_kcalloc(&pdev->dev, SAMPLE_NR,
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sizeof(struct value_to_freq), GFP_KERNEL);
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if (!rtc->val_to_freq)
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return -ENOMEM;
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spin_lock_init(&rtc->lock);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc");
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rtc->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(rtc->regs))
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return PTR_ERR(rtc->regs);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc-soc");
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rtc->regs_soc = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(rtc->regs_soc))
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return PTR_ERR(rtc->regs_soc);
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rtc->irq = platform_get_irq(pdev, 0);
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if (rtc->irq < 0) {
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dev_err(&pdev->dev, "no irq\n");
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return rtc->irq;
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}
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if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq,
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0, pdev->name, rtc) < 0) {
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dev_warn(&pdev->dev, "Interrupt not available.\n");
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rtc->irq = -1;
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}
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platform_set_drvdata(pdev, rtc);
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if (rtc->irq != -1) {
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device_init_wakeup(&pdev->dev, 1);
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ops = &armada38x_rtc_ops;
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} else {
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/*
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* If there is no interrupt available then we can't
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* use the alarm
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*/
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ops = &armada38x_rtc_ops_noirq;
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}
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/* Update RTC-MBUS bridge timing parameters */
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rtc_update_mbus_timing_params(rtc);
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rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
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ops, THIS_MODULE);
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if (IS_ERR(rtc->rtc_dev)) {
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ret = PTR_ERR(rtc->rtc_dev);
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dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
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return ret;
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}
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int armada38x_rtc_suspend(struct device *dev)
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{
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if (device_may_wakeup(dev)) {
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struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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return enable_irq_wake(rtc->irq);
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}
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return 0;
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}
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static int armada38x_rtc_resume(struct device *dev)
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{
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if (device_may_wakeup(dev)) {
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struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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/* Update RTC-MBUS bridge timing parameters */
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rtc_update_mbus_timing_params(rtc);
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return disable_irq_wake(rtc->irq);
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}
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops,
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armada38x_rtc_suspend, armada38x_rtc_resume);
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#ifdef CONFIG_OF
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static const struct of_device_id armada38x_rtc_of_match_table[] = {
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{ .compatible = "marvell,armada-380-rtc", },
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{}
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};
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MODULE_DEVICE_TABLE(of, armada38x_rtc_of_match_table);
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#endif
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static struct platform_driver armada38x_rtc_driver = {
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.driver = {
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.name = "armada38x-rtc",
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.pm = &armada38x_rtc_pm_ops,
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.of_match_table = of_match_ptr(armada38x_rtc_of_match_table),
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},
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};
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module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe);
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MODULE_DESCRIPTION("Marvell Armada 38x RTC driver");
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MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
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MODULE_LICENSE("GPL");
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