forked from Minki/linux
0cf55c21ec
Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
907 lines
24 KiB
C
907 lines
24 KiB
C
/*
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* Copyright (c) 2008-2009 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/slab.h>
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#include "ath9k.h"
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static char *dev_info = "ath9k";
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MODULE_AUTHOR("Atheros Communications");
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MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
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MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
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MODULE_LICENSE("Dual BSD/GPL");
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static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
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module_param_named(debug, ath9k_debug, uint, 0);
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MODULE_PARM_DESC(debug, "Debugging mask");
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int ath9k_modparam_nohwcrypt;
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module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
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MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
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int led_blink;
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module_param_named(blink, led_blink, int, 0444);
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MODULE_PARM_DESC(blink, "Enable LED blink on activity");
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static int ath9k_btcoex_enable;
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module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
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MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
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bool is_ath9k_unloaded;
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/* We use the hw_value as an index into our private channel structure */
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#define CHAN2G(_freq, _idx) { \
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.band = IEEE80211_BAND_2GHZ, \
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.center_freq = (_freq), \
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.hw_value = (_idx), \
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.max_power = 20, \
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}
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#define CHAN5G(_freq, _idx) { \
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.band = IEEE80211_BAND_5GHZ, \
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.center_freq = (_freq), \
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.hw_value = (_idx), \
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.max_power = 20, \
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}
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/* Some 2 GHz radios are actually tunable on 2312-2732
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* on 5 MHz steps, we support the channels which we know
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* we have calibration data for all cards though to make
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* this static */
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static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
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CHAN2G(2412, 0), /* Channel 1 */
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CHAN2G(2417, 1), /* Channel 2 */
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CHAN2G(2422, 2), /* Channel 3 */
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CHAN2G(2427, 3), /* Channel 4 */
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CHAN2G(2432, 4), /* Channel 5 */
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CHAN2G(2437, 5), /* Channel 6 */
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CHAN2G(2442, 6), /* Channel 7 */
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CHAN2G(2447, 7), /* Channel 8 */
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CHAN2G(2452, 8), /* Channel 9 */
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CHAN2G(2457, 9), /* Channel 10 */
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CHAN2G(2462, 10), /* Channel 11 */
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CHAN2G(2467, 11), /* Channel 12 */
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CHAN2G(2472, 12), /* Channel 13 */
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CHAN2G(2484, 13), /* Channel 14 */
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};
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/* Some 5 GHz radios are actually tunable on XXXX-YYYY
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* on 5 MHz steps, we support the channels which we know
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* we have calibration data for all cards though to make
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* this static */
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static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
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/* _We_ call this UNII 1 */
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CHAN5G(5180, 14), /* Channel 36 */
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CHAN5G(5200, 15), /* Channel 40 */
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CHAN5G(5220, 16), /* Channel 44 */
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CHAN5G(5240, 17), /* Channel 48 */
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/* _We_ call this UNII 2 */
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CHAN5G(5260, 18), /* Channel 52 */
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CHAN5G(5280, 19), /* Channel 56 */
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CHAN5G(5300, 20), /* Channel 60 */
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CHAN5G(5320, 21), /* Channel 64 */
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/* _We_ call this "Middle band" */
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CHAN5G(5500, 22), /* Channel 100 */
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CHAN5G(5520, 23), /* Channel 104 */
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CHAN5G(5540, 24), /* Channel 108 */
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CHAN5G(5560, 25), /* Channel 112 */
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CHAN5G(5580, 26), /* Channel 116 */
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CHAN5G(5600, 27), /* Channel 120 */
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CHAN5G(5620, 28), /* Channel 124 */
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CHAN5G(5640, 29), /* Channel 128 */
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CHAN5G(5660, 30), /* Channel 132 */
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CHAN5G(5680, 31), /* Channel 136 */
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CHAN5G(5700, 32), /* Channel 140 */
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/* _We_ call this UNII 3 */
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CHAN5G(5745, 33), /* Channel 149 */
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CHAN5G(5765, 34), /* Channel 153 */
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CHAN5G(5785, 35), /* Channel 157 */
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CHAN5G(5805, 36), /* Channel 161 */
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CHAN5G(5825, 37), /* Channel 165 */
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};
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/* Atheros hardware rate code addition for short premble */
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#define SHPCHECK(__hw_rate, __flags) \
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((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
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#define RATE(_bitrate, _hw_rate, _flags) { \
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.bitrate = (_bitrate), \
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.flags = (_flags), \
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.hw_value = (_hw_rate), \
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.hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
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}
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static struct ieee80211_rate ath9k_legacy_rates[] = {
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RATE(10, 0x1b, 0),
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RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
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RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
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RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
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RATE(60, 0x0b, 0),
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RATE(90, 0x0f, 0),
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RATE(120, 0x0a, 0),
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RATE(180, 0x0e, 0),
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RATE(240, 0x09, 0),
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RATE(360, 0x0d, 0),
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RATE(480, 0x08, 0),
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RATE(540, 0x0c, 0),
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};
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#ifdef CONFIG_MAC80211_LEDS
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static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
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{ .throughput = 0 * 1024, .blink_time = 334 },
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{ .throughput = 1 * 1024, .blink_time = 260 },
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{ .throughput = 5 * 1024, .blink_time = 220 },
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{ .throughput = 10 * 1024, .blink_time = 190 },
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{ .throughput = 20 * 1024, .blink_time = 170 },
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{ .throughput = 50 * 1024, .blink_time = 150 },
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{ .throughput = 70 * 1024, .blink_time = 130 },
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{ .throughput = 100 * 1024, .blink_time = 110 },
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{ .throughput = 200 * 1024, .blink_time = 80 },
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{ .throughput = 300 * 1024, .blink_time = 50 },
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};
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#endif
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static void ath9k_deinit_softc(struct ath_softc *sc);
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/*
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* Read and write, they both share the same lock. We do this to serialize
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* reads and writes on Atheros 802.11n PCI devices only. This is required
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* as the FIFO on these devices can only accept sanely 2 requests.
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*/
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static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
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{
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struct ath_hw *ah = (struct ath_hw *) hw_priv;
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath_softc *sc = (struct ath_softc *) common->priv;
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if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
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unsigned long flags;
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spin_lock_irqsave(&sc->sc_serial_rw, flags);
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iowrite32(val, sc->mem + reg_offset);
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spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
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} else
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iowrite32(val, sc->mem + reg_offset);
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}
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static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
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{
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struct ath_hw *ah = (struct ath_hw *) hw_priv;
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath_softc *sc = (struct ath_softc *) common->priv;
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u32 val;
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if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
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unsigned long flags;
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spin_lock_irqsave(&sc->sc_serial_rw, flags);
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val = ioread32(sc->mem + reg_offset);
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spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
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} else
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val = ioread32(sc->mem + reg_offset);
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return val;
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}
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static const struct ath_ops ath9k_common_ops = {
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.read = ath9k_ioread32,
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.write = ath9k_iowrite32,
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};
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/**************************/
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/* Initialization */
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/**************************/
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static void setup_ht_cap(struct ath_softc *sc,
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struct ieee80211_sta_ht_cap *ht_info)
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{
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struct ath_hw *ah = sc->sc_ah;
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struct ath_common *common = ath9k_hw_common(ah);
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u8 tx_streams, rx_streams;
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int i, max_streams;
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ht_info->ht_supported = true;
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ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
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IEEE80211_HT_CAP_SM_PS |
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IEEE80211_HT_CAP_SGI_40 |
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IEEE80211_HT_CAP_DSSSCCK40;
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if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
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ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
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if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
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ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
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ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
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ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
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if (AR_SREV_9485(ah))
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max_streams = 1;
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else if (AR_SREV_9300_20_OR_LATER(ah))
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max_streams = 3;
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else
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max_streams = 2;
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if (AR_SREV_9280_20_OR_LATER(ah)) {
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if (max_streams >= 2)
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ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
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ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
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}
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/* set up supported mcs set */
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memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
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tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams);
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rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams);
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ath_dbg(common, ATH_DBG_CONFIG,
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"TX streams %d, RX streams: %d\n",
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tx_streams, rx_streams);
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if (tx_streams != rx_streams) {
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ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
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ht_info->mcs.tx_params |= ((tx_streams - 1) <<
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IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
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}
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for (i = 0; i < rx_streams; i++)
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ht_info->mcs.rx_mask[i] = 0xff;
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ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
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}
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static int ath9k_reg_notifier(struct wiphy *wiphy,
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struct regulatory_request *request)
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{
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struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
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struct ath_softc *sc = hw->priv;
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struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
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return ath_reg_notifier_apply(wiphy, request, reg);
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}
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/*
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* This function will allocate both the DMA descriptor structure, and the
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* buffers it contains. These are used to contain the descriptors used
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* by the system.
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*/
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int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
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struct list_head *head, const char *name,
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int nbuf, int ndesc, bool is_tx)
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{
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#define DS2PHYS(_dd, _ds) \
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((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
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#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
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#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
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struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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u8 *ds;
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struct ath_buf *bf;
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int i, bsize, error, desc_len;
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ath_dbg(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
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name, nbuf, ndesc);
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INIT_LIST_HEAD(head);
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if (is_tx)
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desc_len = sc->sc_ah->caps.tx_desc_len;
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else
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desc_len = sizeof(struct ath_desc);
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/* ath_desc must be a multiple of DWORDs */
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if ((desc_len % 4) != 0) {
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ath_err(common, "ath_desc not DWORD aligned\n");
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BUG_ON((desc_len % 4) != 0);
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error = -ENOMEM;
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goto fail;
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}
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dd->dd_desc_len = desc_len * nbuf * ndesc;
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/*
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* Need additional DMA memory because we can't use
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* descriptors that cross the 4K page boundary. Assume
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* one skipped descriptor per 4K page.
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*/
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if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
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u32 ndesc_skipped =
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ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
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u32 dma_len;
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while (ndesc_skipped) {
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dma_len = ndesc_skipped * desc_len;
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dd->dd_desc_len += dma_len;
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ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
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}
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}
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/* allocate descriptors */
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dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
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&dd->dd_desc_paddr, GFP_KERNEL);
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if (dd->dd_desc == NULL) {
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error = -ENOMEM;
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goto fail;
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}
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ds = (u8 *) dd->dd_desc;
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ath_dbg(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
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name, ds, (u32) dd->dd_desc_len,
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ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
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/* allocate buffers */
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bsize = sizeof(struct ath_buf) * nbuf;
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bf = kzalloc(bsize, GFP_KERNEL);
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if (bf == NULL) {
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error = -ENOMEM;
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goto fail2;
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}
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dd->dd_bufptr = bf;
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for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
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bf->bf_desc = ds;
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bf->bf_daddr = DS2PHYS(dd, ds);
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if (!(sc->sc_ah->caps.hw_caps &
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ATH9K_HW_CAP_4KB_SPLITTRANS)) {
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/*
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* Skip descriptor addresses which can cause 4KB
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* boundary crossing (addr + length) with a 32 dword
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* descriptor fetch.
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*/
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while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
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BUG_ON((caddr_t) bf->bf_desc >=
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((caddr_t) dd->dd_desc +
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dd->dd_desc_len));
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ds += (desc_len * ndesc);
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bf->bf_desc = ds;
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bf->bf_daddr = DS2PHYS(dd, ds);
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}
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}
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list_add_tail(&bf->list, head);
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}
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return 0;
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fail2:
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dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
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dd->dd_desc_paddr);
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fail:
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memset(dd, 0, sizeof(*dd));
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return error;
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#undef ATH_DESC_4KB_BOUND_CHECK
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#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
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#undef DS2PHYS
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}
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void ath9k_init_crypto(struct ath_softc *sc)
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{
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struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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int i = 0;
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/* Get the hardware key cache size. */
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common->keymax = sc->sc_ah->caps.keycache_size;
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if (common->keymax > ATH_KEYMAX) {
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ath_dbg(common, ATH_DBG_ANY,
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"Warning, using only %u entries in %u key cache\n",
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ATH_KEYMAX, common->keymax);
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common->keymax = ATH_KEYMAX;
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}
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/*
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* Reset the key cache since some parts do not
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* reset the contents on initial power up.
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*/
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for (i = 0; i < common->keymax; i++)
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ath_hw_keyreset(common, (u16) i);
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/*
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* Check whether the separate key cache entries
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* are required to handle both tx+rx MIC keys.
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* With split mic keys the number of stations is limited
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* to 27 otherwise 59.
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*/
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if (sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
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common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
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}
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static int ath9k_init_btcoex(struct ath_softc *sc)
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{
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struct ath_txq *txq;
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int r;
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switch (sc->sc_ah->btcoex_hw.scheme) {
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case ATH_BTCOEX_CFG_NONE:
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break;
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case ATH_BTCOEX_CFG_2WIRE:
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ath9k_hw_btcoex_init_2wire(sc->sc_ah);
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break;
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case ATH_BTCOEX_CFG_3WIRE:
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ath9k_hw_btcoex_init_3wire(sc->sc_ah);
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r = ath_init_btcoex_timer(sc);
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if (r)
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return -1;
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txq = sc->tx.txq_map[WME_AC_BE];
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ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum);
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sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
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break;
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default:
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WARN_ON(1);
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break;
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}
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return 0;
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}
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|
|
static int ath9k_init_queues(struct ath_softc *sc)
|
|
{
|
|
int i = 0;
|
|
|
|
sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
|
|
sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
|
|
|
|
sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
|
|
ath_cabq_update(sc);
|
|
|
|
for (i = 0; i < WME_NUM_AC; i++) {
|
|
sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
|
|
sc->tx.txq_map[i]->mac80211_qnum = i;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int ath9k_init_channels_rates(struct ath_softc *sc)
|
|
{
|
|
void *channels;
|
|
|
|
BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +
|
|
ARRAY_SIZE(ath9k_5ghz_chantable) !=
|
|
ATH9K_NUM_CHANNELS);
|
|
|
|
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
|
|
channels = kmemdup(ath9k_2ghz_chantable,
|
|
sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
|
|
if (!channels)
|
|
return -ENOMEM;
|
|
|
|
sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
|
|
sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
|
|
sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
|
|
ARRAY_SIZE(ath9k_2ghz_chantable);
|
|
sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
|
|
sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
|
|
ARRAY_SIZE(ath9k_legacy_rates);
|
|
}
|
|
|
|
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
|
|
channels = kmemdup(ath9k_5ghz_chantable,
|
|
sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
|
|
if (!channels) {
|
|
if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
|
|
kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
|
|
sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
|
|
sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
|
|
ARRAY_SIZE(ath9k_5ghz_chantable);
|
|
sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
|
|
ath9k_legacy_rates + 4;
|
|
sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
|
|
ARRAY_SIZE(ath9k_legacy_rates) - 4;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void ath9k_init_misc(struct ath_softc *sc)
|
|
{
|
|
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
|
int i = 0;
|
|
|
|
setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
|
|
|
|
sc->config.txpowlimit = ATH_TXPOWER_MAX;
|
|
|
|
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
|
|
sc->sc_flags |= SC_OP_TXAGGR;
|
|
sc->sc_flags |= SC_OP_RXAGGR;
|
|
}
|
|
|
|
common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
|
|
common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
|
|
|
|
ath9k_hw_set_diversity(sc->sc_ah, true);
|
|
sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
|
|
|
|
memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
|
|
|
|
sc->beacon.slottime = ATH9K_SLOT_TIME_9;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
|
|
sc->beacon.bslot[i] = NULL;
|
|
|
|
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
|
|
sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
|
|
}
|
|
|
|
static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
|
|
const struct ath_bus_ops *bus_ops)
|
|
{
|
|
struct ath_hw *ah = NULL;
|
|
struct ath_common *common;
|
|
int ret = 0, i;
|
|
int csz = 0;
|
|
|
|
ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
|
|
if (!ah)
|
|
return -ENOMEM;
|
|
|
|
ah->hw = sc->hw;
|
|
ah->hw_version.devid = devid;
|
|
ah->hw_version.subsysid = subsysid;
|
|
sc->sc_ah = ah;
|
|
|
|
if (!sc->dev->platform_data)
|
|
ah->ah_flags |= AH_USE_EEPROM;
|
|
|
|
common = ath9k_hw_common(ah);
|
|
common->ops = &ath9k_common_ops;
|
|
common->bus_ops = bus_ops;
|
|
common->ah = ah;
|
|
common->hw = sc->hw;
|
|
common->priv = sc;
|
|
common->debug_mask = ath9k_debug;
|
|
common->btcoex_enabled = ath9k_btcoex_enable == 1;
|
|
spin_lock_init(&common->cc_lock);
|
|
|
|
spin_lock_init(&sc->sc_serial_rw);
|
|
spin_lock_init(&sc->sc_pm_lock);
|
|
mutex_init(&sc->mutex);
|
|
#ifdef CONFIG_ATH9K_DEBUGFS
|
|
spin_lock_init(&sc->nodes_lock);
|
|
INIT_LIST_HEAD(&sc->nodes);
|
|
#endif
|
|
tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
|
|
tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
|
|
(unsigned long)sc);
|
|
|
|
/*
|
|
* Cache line size is used to size and align various
|
|
* structures used to communicate with the hardware.
|
|
*/
|
|
ath_read_cachesize(common, &csz);
|
|
common->cachelsz = csz << 2; /* convert to bytes */
|
|
|
|
/* Initializes the hardware for all supported chipsets */
|
|
ret = ath9k_hw_init(ah);
|
|
if (ret)
|
|
goto err_hw;
|
|
|
|
ret = ath9k_init_queues(sc);
|
|
if (ret)
|
|
goto err_queues;
|
|
|
|
ret = ath9k_init_btcoex(sc);
|
|
if (ret)
|
|
goto err_btcoex;
|
|
|
|
ret = ath9k_init_channels_rates(sc);
|
|
if (ret)
|
|
goto err_btcoex;
|
|
|
|
ath9k_init_crypto(sc);
|
|
ath9k_init_misc(sc);
|
|
|
|
return 0;
|
|
|
|
err_btcoex:
|
|
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
|
|
if (ATH_TXQ_SETUP(sc, i))
|
|
ath_tx_cleanupq(sc, &sc->tx.txq[i]);
|
|
err_queues:
|
|
ath9k_hw_deinit(ah);
|
|
err_hw:
|
|
|
|
kfree(ah);
|
|
sc->sc_ah = NULL;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
|
|
{
|
|
struct ieee80211_supported_band *sband;
|
|
struct ieee80211_channel *chan;
|
|
struct ath_hw *ah = sc->sc_ah;
|
|
struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
|
|
int i;
|
|
|
|
sband = &sc->sbands[band];
|
|
for (i = 0; i < sband->n_channels; i++) {
|
|
chan = &sband->channels[i];
|
|
ah->curchan = &ah->channels[chan->hw_value];
|
|
ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20);
|
|
ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
|
|
chan->max_power = reg->max_power_level / 2;
|
|
}
|
|
}
|
|
|
|
static void ath9k_init_txpower_limits(struct ath_softc *sc)
|
|
{
|
|
struct ath_hw *ah = sc->sc_ah;
|
|
struct ath9k_channel *curchan = ah->curchan;
|
|
|
|
if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
|
|
ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
|
|
if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
|
|
ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
|
|
|
|
ah->curchan = curchan;
|
|
}
|
|
|
|
void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
|
|
{
|
|
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
|
|
|
hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
|
|
IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
|
|
IEEE80211_HW_SIGNAL_DBM |
|
|
IEEE80211_HW_SUPPORTS_PS |
|
|
IEEE80211_HW_PS_NULLFUNC_STACK |
|
|
IEEE80211_HW_SPECTRUM_MGMT |
|
|
IEEE80211_HW_REPORTS_TX_ACK_STATUS;
|
|
|
|
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
|
|
hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
|
|
|
|
if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
|
|
hw->flags |= IEEE80211_HW_MFP_CAPABLE;
|
|
|
|
hw->wiphy->interface_modes =
|
|
BIT(NL80211_IFTYPE_P2P_GO) |
|
|
BIT(NL80211_IFTYPE_P2P_CLIENT) |
|
|
BIT(NL80211_IFTYPE_AP) |
|
|
BIT(NL80211_IFTYPE_WDS) |
|
|
BIT(NL80211_IFTYPE_STATION) |
|
|
BIT(NL80211_IFTYPE_ADHOC) |
|
|
BIT(NL80211_IFTYPE_MESH_POINT);
|
|
|
|
if (AR_SREV_5416(sc->sc_ah))
|
|
hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
|
|
|
|
hw->queues = 4;
|
|
hw->max_rates = 4;
|
|
hw->channel_change_time = 5000;
|
|
hw->max_listen_interval = 10;
|
|
hw->max_rate_tries = 10;
|
|
hw->sta_data_size = sizeof(struct ath_node);
|
|
hw->vif_data_size = sizeof(struct ath_vif);
|
|
|
|
#ifdef CONFIG_ATH9K_RATE_CONTROL
|
|
hw->rate_control_algorithm = "ath9k_rate_control";
|
|
#endif
|
|
|
|
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
|
|
hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
|
|
&sc->sbands[IEEE80211_BAND_2GHZ];
|
|
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
|
|
hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
|
|
&sc->sbands[IEEE80211_BAND_5GHZ];
|
|
|
|
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
|
|
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
|
|
setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
|
|
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
|
|
setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
|
|
}
|
|
|
|
SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
|
|
}
|
|
|
|
int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
|
|
const struct ath_bus_ops *bus_ops)
|
|
{
|
|
struct ieee80211_hw *hw = sc->hw;
|
|
struct ath_common *common;
|
|
struct ath_hw *ah;
|
|
int error = 0;
|
|
struct ath_regulatory *reg;
|
|
|
|
/* Bring up device */
|
|
error = ath9k_init_softc(devid, sc, subsysid, bus_ops);
|
|
if (error != 0)
|
|
goto error_init;
|
|
|
|
ah = sc->sc_ah;
|
|
common = ath9k_hw_common(ah);
|
|
ath9k_set_hw_capab(sc, hw);
|
|
|
|
/* Initialize regulatory */
|
|
error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
|
|
ath9k_reg_notifier);
|
|
if (error)
|
|
goto error_regd;
|
|
|
|
reg = &common->regulatory;
|
|
|
|
/* Setup TX DMA */
|
|
error = ath_tx_init(sc, ATH_TXBUF);
|
|
if (error != 0)
|
|
goto error_tx;
|
|
|
|
/* Setup RX DMA */
|
|
error = ath_rx_init(sc, ATH_RXBUF);
|
|
if (error != 0)
|
|
goto error_rx;
|
|
|
|
ath9k_init_txpower_limits(sc);
|
|
|
|
#ifdef CONFIG_MAC80211_LEDS
|
|
/* must be initialized before ieee80211_register_hw */
|
|
sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
|
|
IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
|
|
ARRAY_SIZE(ath9k_tpt_blink));
|
|
#endif
|
|
|
|
/* Register with mac80211 */
|
|
error = ieee80211_register_hw(hw);
|
|
if (error)
|
|
goto error_register;
|
|
|
|
error = ath9k_init_debug(ah);
|
|
if (error) {
|
|
ath_err(common, "Unable to create debugfs files\n");
|
|
goto error_world;
|
|
}
|
|
|
|
/* Handle world regulatory */
|
|
if (!ath_is_world_regd(reg)) {
|
|
error = regulatory_hint(hw->wiphy, reg->alpha2);
|
|
if (error)
|
|
goto error_world;
|
|
}
|
|
|
|
INIT_WORK(&sc->hw_check_work, ath_hw_check);
|
|
INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
|
|
sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
|
|
|
|
ath_init_leds(sc);
|
|
ath_start_rfkill_poll(sc);
|
|
|
|
return 0;
|
|
|
|
error_world:
|
|
ieee80211_unregister_hw(hw);
|
|
error_register:
|
|
ath_rx_cleanup(sc);
|
|
error_rx:
|
|
ath_tx_cleanup(sc);
|
|
error_tx:
|
|
/* Nothing */
|
|
error_regd:
|
|
ath9k_deinit_softc(sc);
|
|
error_init:
|
|
return error;
|
|
}
|
|
|
|
/*****************************/
|
|
/* De-Initialization */
|
|
/*****************************/
|
|
|
|
static void ath9k_deinit_softc(struct ath_softc *sc)
|
|
{
|
|
int i = 0;
|
|
|
|
if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
|
|
kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
|
|
|
|
if (sc->sbands[IEEE80211_BAND_5GHZ].channels)
|
|
kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels);
|
|
|
|
if ((sc->btcoex.no_stomp_timer) &&
|
|
sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
|
|
ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
|
|
|
|
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
|
|
if (ATH_TXQ_SETUP(sc, i))
|
|
ath_tx_cleanupq(sc, &sc->tx.txq[i]);
|
|
|
|
ath9k_hw_deinit(sc->sc_ah);
|
|
|
|
kfree(sc->sc_ah);
|
|
sc->sc_ah = NULL;
|
|
}
|
|
|
|
void ath9k_deinit_device(struct ath_softc *sc)
|
|
{
|
|
struct ieee80211_hw *hw = sc->hw;
|
|
|
|
ath9k_ps_wakeup(sc);
|
|
|
|
wiphy_rfkill_stop_polling(sc->hw->wiphy);
|
|
ath_deinit_leds(sc);
|
|
|
|
ath9k_ps_restore(sc);
|
|
|
|
ieee80211_unregister_hw(hw);
|
|
ath_rx_cleanup(sc);
|
|
ath_tx_cleanup(sc);
|
|
ath9k_deinit_softc(sc);
|
|
}
|
|
|
|
void ath_descdma_cleanup(struct ath_softc *sc,
|
|
struct ath_descdma *dd,
|
|
struct list_head *head)
|
|
{
|
|
dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
|
|
dd->dd_desc_paddr);
|
|
|
|
INIT_LIST_HEAD(head);
|
|
kfree(dd->dd_bufptr);
|
|
memset(dd, 0, sizeof(*dd));
|
|
}
|
|
|
|
/************************/
|
|
/* Module Hooks */
|
|
/************************/
|
|
|
|
static int __init ath9k_init(void)
|
|
{
|
|
int error;
|
|
|
|
/* Register rate control algorithm */
|
|
error = ath_rate_control_register();
|
|
if (error != 0) {
|
|
printk(KERN_ERR
|
|
"ath9k: Unable to register rate control "
|
|
"algorithm: %d\n",
|
|
error);
|
|
goto err_out;
|
|
}
|
|
|
|
error = ath_pci_init();
|
|
if (error < 0) {
|
|
printk(KERN_ERR
|
|
"ath9k: No PCI devices found, driver not installed.\n");
|
|
error = -ENODEV;
|
|
goto err_rate_unregister;
|
|
}
|
|
|
|
error = ath_ahb_init();
|
|
if (error < 0) {
|
|
error = -ENODEV;
|
|
goto err_pci_exit;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_pci_exit:
|
|
ath_pci_exit();
|
|
|
|
err_rate_unregister:
|
|
ath_rate_control_unregister();
|
|
err_out:
|
|
return error;
|
|
}
|
|
module_init(ath9k_init);
|
|
|
|
static void __exit ath9k_exit(void)
|
|
{
|
|
is_ath9k_unloaded = true;
|
|
ath_ahb_exit();
|
|
ath_pci_exit();
|
|
ath_rate_control_unregister();
|
|
printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
|
|
}
|
|
module_exit(ath9k_exit);
|