Manuel Lauss 69e4e63ec8 MIPS: Alchemy: Fix cpu clock calculation ... The current code uses bits 0-6 of the sys_cpupll register to calculate core clock speed. However this is only valid on Au1300, on all earlier models the hardware only uses bits 0-5 to generate core clock. This fixes clock calculation on the MTX1 (Au1500), where bit 6 of cpupll is set as well, which ultimately lead the code to calculate a bogus cpu core clock and also uart base clock down the line. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Reported-by: John Crispin <blogic@openwrt.org> Tested-by: Bruno Randolf <br1@einfach.org> Cc: stable@vger.kernel.org [v3.17+] Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/9279/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2015-02-20 13:01:42 +01:00
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common	MIPS: Alchemy: Fix cpu clock calculation	2015-02-20 13:01:42 +01:00
devboards	MIPS: Alchemy: DB1300: Add touch penirq support	2014-09-22 13:35:47 +02:00
board-gpr.c	MIPS: Alchemy: Fix unchecked kstrtoul return value	2014-03-06 20:52:28 +01:00
board-mtx1.c	MIPS: Alchemy: introduce helpers to access SYS register block.	2014-07-30 13:53:28 +02:00
board-xxs1500.c	MIPS: Alchemy: introduce helpers to access SYS register block.	2014-07-30 13:53:28 +02:00
Kconfig	MIPS: Alchemy: Unify Devboard support.	2014-03-26 23:09:21 +01:00
Makefile	MIPS: Alchemy: merge GPR/MTX-1/XXS1500 board code into single files	2011-12-07 22:02:06 +00:00
Platform	MIPS: Alchemy: Unify Devboard support.	2014-03-26 23:09:21 +01:00