444a0fea51
PSP has issue for renoir, that will cause VCN fw failed to be loaded. So use direct loading for the moment till the issue is addressed. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
806 lines
20 KiB
C
806 lines
20 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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#include <linux/firmware.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <drm/drm.h>
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#include "amdgpu.h"
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#include "amdgpu_pm.h"
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#include "amdgpu_vcn.h"
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#include "soc15d.h"
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#include "soc15_common.h"
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#include "vcn/vcn_1_0_offset.h"
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#include "vcn/vcn_1_0_sh_mask.h"
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/* 1 second timeout */
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#define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000)
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/* Firmware Names */
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#define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin"
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#define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin"
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#define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin"
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#define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin"
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#define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin"
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#define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin"
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#define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin"
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#define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin"
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MODULE_FIRMWARE(FIRMWARE_RAVEN);
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MODULE_FIRMWARE(FIRMWARE_PICASSO);
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MODULE_FIRMWARE(FIRMWARE_RAVEN2);
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MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
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MODULE_FIRMWARE(FIRMWARE_RENOIR);
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MODULE_FIRMWARE(FIRMWARE_NAVI10);
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MODULE_FIRMWARE(FIRMWARE_NAVI14);
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MODULE_FIRMWARE(FIRMWARE_NAVI12);
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static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
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int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
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{
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unsigned long bo_size;
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const char *fw_name;
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const struct common_firmware_header *hdr;
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unsigned char fw_check;
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int i, r;
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INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
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switch (adev->asic_type) {
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case CHIP_RAVEN:
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if (adev->rev_id >= 8)
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fw_name = FIRMWARE_RAVEN2;
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else if (adev->pdev->device == 0x15d8)
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fw_name = FIRMWARE_PICASSO;
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else
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fw_name = FIRMWARE_RAVEN;
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break;
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case CHIP_ARCTURUS:
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fw_name = FIRMWARE_ARCTURUS;
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break;
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case CHIP_RENOIR:
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fw_name = FIRMWARE_RENOIR;
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if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
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(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
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adev->vcn.indirect_sram = true;
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break;
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case CHIP_NAVI10:
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fw_name = FIRMWARE_NAVI10;
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if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
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(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
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adev->vcn.indirect_sram = true;
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break;
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case CHIP_NAVI14:
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fw_name = FIRMWARE_NAVI14;
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if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
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(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) &&
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adev->asic_type != CHIP_RENOIR) /* to be removed while vcn psp loading works */
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adev->vcn.indirect_sram = true;
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break;
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case CHIP_NAVI12:
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fw_name = FIRMWARE_NAVI12;
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if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
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(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
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adev->vcn.indirect_sram = true;
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break;
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default:
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return -EINVAL;
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}
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r = request_firmware(&adev->vcn.fw, fw_name, adev->dev);
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if (r) {
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dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
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fw_name);
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return r;
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}
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r = amdgpu_ucode_validate(adev->vcn.fw);
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if (r) {
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dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n",
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fw_name);
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release_firmware(adev->vcn.fw);
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adev->vcn.fw = NULL;
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return r;
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}
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hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
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adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
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/* Bit 20-23, it is encode major and non-zero for new naming convention.
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* This field is part of version minor and DRM_DISABLED_FLAG in old naming
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* convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
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* is zero in old naming convention, this field is always zero so far.
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* These four bits are used to tell which naming convention is present.
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*/
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fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
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if (fw_check) {
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unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
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fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
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enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
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enc_major = fw_check;
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dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
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vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
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DRM_INFO("Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n",
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enc_major, enc_minor, dec_ver, vep, fw_rev);
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} else {
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unsigned int version_major, version_minor, family_id;
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family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
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version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
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version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
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DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n",
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version_major, version_minor, family_id);
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}
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bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
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if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
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adev->asic_type == CHIP_RENOIR)
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bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
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for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
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if (adev->vcn.harvest_config & (1 << i))
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continue;
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r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo,
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&adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr);
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if (r) {
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dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
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return r;
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}
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}
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if (adev->vcn.indirect_sram) {
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r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.dpg_sram_bo,
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&adev->vcn.dpg_sram_gpu_addr, &adev->vcn.dpg_sram_cpu_addr);
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if (r) {
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dev_err(adev->dev, "(%d) failed to allocate DPG bo\n", r);
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return r;
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}
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}
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return 0;
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}
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int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
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{
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int i, j;
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if (adev->vcn.indirect_sram) {
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amdgpu_bo_free_kernel(&adev->vcn.dpg_sram_bo,
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&adev->vcn.dpg_sram_gpu_addr,
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(void **)&adev->vcn.dpg_sram_cpu_addr);
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}
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for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
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if (adev->vcn.harvest_config & (1 << j))
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continue;
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kvfree(adev->vcn.inst[j].saved_bo);
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amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
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&adev->vcn.inst[j].gpu_addr,
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(void **)&adev->vcn.inst[j].cpu_addr);
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amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
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for (i = 0; i < adev->vcn.num_enc_rings; ++i)
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amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
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amdgpu_ring_fini(&adev->vcn.inst[j].ring_jpeg);
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}
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release_firmware(adev->vcn.fw);
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return 0;
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}
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int amdgpu_vcn_suspend(struct amdgpu_device *adev)
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{
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unsigned size;
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void *ptr;
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int i;
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cancel_delayed_work_sync(&adev->vcn.idle_work);
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for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
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if (adev->vcn.harvest_config & (1 << i))
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continue;
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if (adev->vcn.inst[i].vcpu_bo == NULL)
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return 0;
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size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
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ptr = adev->vcn.inst[i].cpu_addr;
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adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
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if (!adev->vcn.inst[i].saved_bo)
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return -ENOMEM;
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memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
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}
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return 0;
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}
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int amdgpu_vcn_resume(struct amdgpu_device *adev)
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{
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unsigned size;
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void *ptr;
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int i;
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for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
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if (adev->vcn.harvest_config & (1 << i))
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continue;
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if (adev->vcn.inst[i].vcpu_bo == NULL)
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return -EINVAL;
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size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
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ptr = adev->vcn.inst[i].cpu_addr;
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if (adev->vcn.inst[i].saved_bo != NULL) {
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memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
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kvfree(adev->vcn.inst[i].saved_bo);
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adev->vcn.inst[i].saved_bo = NULL;
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} else {
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const struct common_firmware_header *hdr;
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unsigned offset;
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hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
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if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
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adev->asic_type == CHIP_RENOIR) {
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offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
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memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
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le32_to_cpu(hdr->ucode_size_bytes));
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size -= le32_to_cpu(hdr->ucode_size_bytes);
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ptr += le32_to_cpu(hdr->ucode_size_bytes);
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}
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memset_io(ptr, 0, size);
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}
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}
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return 0;
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}
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static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
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{
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struct amdgpu_device *adev =
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container_of(work, struct amdgpu_device, vcn.idle_work.work);
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unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
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unsigned int i, j;
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for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
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if (adev->vcn.harvest_config & (1 << j))
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continue;
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for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
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fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
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}
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if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
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struct dpg_pause_state new_state;
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if (fence[j])
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new_state.fw_based = VCN_DPG_STATE__PAUSE;
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else
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new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
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if (amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg))
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new_state.jpeg = VCN_DPG_STATE__PAUSE;
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else
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new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
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adev->vcn.pause_dpg_mode(adev, &new_state);
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}
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fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg);
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fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
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fences += fence[j];
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}
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if (fences == 0) {
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amdgpu_gfx_off_ctrl(adev, true);
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if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled)
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amdgpu_dpm_enable_uvd(adev, false);
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else
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amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
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AMD_PG_STATE_GATE);
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} else {
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schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
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}
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}
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void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
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if (set_clocks) {
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amdgpu_gfx_off_ctrl(adev, false);
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if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled)
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amdgpu_dpm_enable_uvd(adev, true);
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else
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amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
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AMD_PG_STATE_UNGATE);
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}
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if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
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struct dpg_pause_state new_state;
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unsigned int fences = 0;
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unsigned int i;
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for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
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fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
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}
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if (fences)
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new_state.fw_based = VCN_DPG_STATE__PAUSE;
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else
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new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
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if (amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_jpeg))
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new_state.jpeg = VCN_DPG_STATE__PAUSE;
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else
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new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
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if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
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new_state.fw_based = VCN_DPG_STATE__PAUSE;
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else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
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new_state.jpeg = VCN_DPG_STATE__PAUSE;
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adev->vcn.pause_dpg_mode(adev, &new_state);
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}
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}
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void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
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{
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schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
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}
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int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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uint32_t tmp = 0;
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unsigned i;
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int r;
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WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
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r = amdgpu_ring_alloc(ring, 3);
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if (r)
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return r;
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amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
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amdgpu_ring_write(ring, 0xDEADBEEF);
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amdgpu_ring_commit(ring);
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
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if (tmp == 0xDEADBEEF)
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break;
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udelay(1);
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}
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if (i >= adev->usec_timeout)
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r = -ETIMEDOUT;
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return r;
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}
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static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
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struct amdgpu_bo *bo,
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struct dma_fence **fence)
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{
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struct amdgpu_device *adev = ring->adev;
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struct dma_fence *f = NULL;
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struct amdgpu_job *job;
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struct amdgpu_ib *ib;
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uint64_t addr;
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int i, r;
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r = amdgpu_job_alloc_with_ib(adev, 64, &job);
|
|
if (r)
|
|
goto err;
|
|
|
|
ib = &job->ibs[0];
|
|
addr = amdgpu_bo_gpu_offset(bo);
|
|
ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
|
|
ib->ptr[1] = addr;
|
|
ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
|
|
ib->ptr[3] = addr >> 32;
|
|
ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
|
|
ib->ptr[5] = 0;
|
|
for (i = 6; i < 16; i += 2) {
|
|
ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
|
|
ib->ptr[i+1] = 0;
|
|
}
|
|
ib->length_dw = 16;
|
|
|
|
r = amdgpu_job_submit_direct(job, ring, &f);
|
|
if (r)
|
|
goto err_free;
|
|
|
|
amdgpu_bo_fence(bo, f, false);
|
|
amdgpu_bo_unreserve(bo);
|
|
amdgpu_bo_unref(&bo);
|
|
|
|
if (fence)
|
|
*fence = dma_fence_get(f);
|
|
dma_fence_put(f);
|
|
|
|
return 0;
|
|
|
|
err_free:
|
|
amdgpu_job_free(job);
|
|
|
|
err:
|
|
amdgpu_bo_unreserve(bo);
|
|
amdgpu_bo_unref(&bo);
|
|
return r;
|
|
}
|
|
|
|
static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
|
|
struct dma_fence **fence)
|
|
{
|
|
struct amdgpu_device *adev = ring->adev;
|
|
struct amdgpu_bo *bo = NULL;
|
|
uint32_t *msg;
|
|
int r, i;
|
|
|
|
r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
|
|
AMDGPU_GEM_DOMAIN_VRAM,
|
|
&bo, NULL, (void **)&msg);
|
|
if (r)
|
|
return r;
|
|
|
|
msg[0] = cpu_to_le32(0x00000028);
|
|
msg[1] = cpu_to_le32(0x00000038);
|
|
msg[2] = cpu_to_le32(0x00000001);
|
|
msg[3] = cpu_to_le32(0x00000000);
|
|
msg[4] = cpu_to_le32(handle);
|
|
msg[5] = cpu_to_le32(0x00000000);
|
|
msg[6] = cpu_to_le32(0x00000001);
|
|
msg[7] = cpu_to_le32(0x00000028);
|
|
msg[8] = cpu_to_le32(0x00000010);
|
|
msg[9] = cpu_to_le32(0x00000000);
|
|
msg[10] = cpu_to_le32(0x00000007);
|
|
msg[11] = cpu_to_le32(0x00000000);
|
|
msg[12] = cpu_to_le32(0x00000780);
|
|
msg[13] = cpu_to_le32(0x00000440);
|
|
for (i = 14; i < 1024; ++i)
|
|
msg[i] = cpu_to_le32(0x0);
|
|
|
|
return amdgpu_vcn_dec_send_msg(ring, bo, fence);
|
|
}
|
|
|
|
static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
|
|
struct dma_fence **fence)
|
|
{
|
|
struct amdgpu_device *adev = ring->adev;
|
|
struct amdgpu_bo *bo = NULL;
|
|
uint32_t *msg;
|
|
int r, i;
|
|
|
|
r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
|
|
AMDGPU_GEM_DOMAIN_VRAM,
|
|
&bo, NULL, (void **)&msg);
|
|
if (r)
|
|
return r;
|
|
|
|
msg[0] = cpu_to_le32(0x00000028);
|
|
msg[1] = cpu_to_le32(0x00000018);
|
|
msg[2] = cpu_to_le32(0x00000000);
|
|
msg[3] = cpu_to_le32(0x00000002);
|
|
msg[4] = cpu_to_le32(handle);
|
|
msg[5] = cpu_to_le32(0x00000000);
|
|
for (i = 6; i < 1024; ++i)
|
|
msg[i] = cpu_to_le32(0x0);
|
|
|
|
return amdgpu_vcn_dec_send_msg(ring, bo, fence);
|
|
}
|
|
|
|
int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
|
|
{
|
|
struct dma_fence *fence;
|
|
long r;
|
|
|
|
r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
|
|
if (r)
|
|
goto error;
|
|
|
|
r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence);
|
|
if (r)
|
|
goto error;
|
|
|
|
r = dma_fence_wait_timeout(fence, false, timeout);
|
|
if (r == 0)
|
|
r = -ETIMEDOUT;
|
|
else if (r > 0)
|
|
r = 0;
|
|
|
|
dma_fence_put(fence);
|
|
error:
|
|
return r;
|
|
}
|
|
|
|
int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
|
|
{
|
|
struct amdgpu_device *adev = ring->adev;
|
|
uint32_t rptr;
|
|
unsigned i;
|
|
int r;
|
|
|
|
r = amdgpu_ring_alloc(ring, 16);
|
|
if (r)
|
|
return r;
|
|
|
|
rptr = amdgpu_ring_get_rptr(ring);
|
|
|
|
amdgpu_ring_write(ring, VCN_ENC_CMD_END);
|
|
amdgpu_ring_commit(ring);
|
|
|
|
for (i = 0; i < adev->usec_timeout; i++) {
|
|
if (amdgpu_ring_get_rptr(ring) != rptr)
|
|
break;
|
|
udelay(1);
|
|
}
|
|
|
|
if (i >= adev->usec_timeout)
|
|
r = -ETIMEDOUT;
|
|
|
|
return r;
|
|
}
|
|
|
|
static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
|
|
struct dma_fence **fence)
|
|
{
|
|
const unsigned ib_size_dw = 16;
|
|
struct amdgpu_job *job;
|
|
struct amdgpu_ib *ib;
|
|
struct dma_fence *f = NULL;
|
|
uint64_t dummy;
|
|
int i, r;
|
|
|
|
r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
|
|
if (r)
|
|
return r;
|
|
|
|
ib = &job->ibs[0];
|
|
dummy = ib->gpu_addr + 1024;
|
|
|
|
ib->length_dw = 0;
|
|
ib->ptr[ib->length_dw++] = 0x00000018;
|
|
ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
|
|
ib->ptr[ib->length_dw++] = handle;
|
|
ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
|
|
ib->ptr[ib->length_dw++] = dummy;
|
|
ib->ptr[ib->length_dw++] = 0x0000000b;
|
|
|
|
ib->ptr[ib->length_dw++] = 0x00000014;
|
|
ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
|
|
ib->ptr[ib->length_dw++] = 0x0000001c;
|
|
ib->ptr[ib->length_dw++] = 0x00000000;
|
|
ib->ptr[ib->length_dw++] = 0x00000000;
|
|
|
|
ib->ptr[ib->length_dw++] = 0x00000008;
|
|
ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
|
|
|
|
for (i = ib->length_dw; i < ib_size_dw; ++i)
|
|
ib->ptr[i] = 0x0;
|
|
|
|
r = amdgpu_job_submit_direct(job, ring, &f);
|
|
if (r)
|
|
goto err;
|
|
|
|
if (fence)
|
|
*fence = dma_fence_get(f);
|
|
dma_fence_put(f);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
amdgpu_job_free(job);
|
|
return r;
|
|
}
|
|
|
|
static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
|
|
struct dma_fence **fence)
|
|
{
|
|
const unsigned ib_size_dw = 16;
|
|
struct amdgpu_job *job;
|
|
struct amdgpu_ib *ib;
|
|
struct dma_fence *f = NULL;
|
|
uint64_t dummy;
|
|
int i, r;
|
|
|
|
r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
|
|
if (r)
|
|
return r;
|
|
|
|
ib = &job->ibs[0];
|
|
dummy = ib->gpu_addr + 1024;
|
|
|
|
ib->length_dw = 0;
|
|
ib->ptr[ib->length_dw++] = 0x00000018;
|
|
ib->ptr[ib->length_dw++] = 0x00000001;
|
|
ib->ptr[ib->length_dw++] = handle;
|
|
ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
|
|
ib->ptr[ib->length_dw++] = dummy;
|
|
ib->ptr[ib->length_dw++] = 0x0000000b;
|
|
|
|
ib->ptr[ib->length_dw++] = 0x00000014;
|
|
ib->ptr[ib->length_dw++] = 0x00000002;
|
|
ib->ptr[ib->length_dw++] = 0x0000001c;
|
|
ib->ptr[ib->length_dw++] = 0x00000000;
|
|
ib->ptr[ib->length_dw++] = 0x00000000;
|
|
|
|
ib->ptr[ib->length_dw++] = 0x00000008;
|
|
ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
|
|
|
|
for (i = ib->length_dw; i < ib_size_dw; ++i)
|
|
ib->ptr[i] = 0x0;
|
|
|
|
r = amdgpu_job_submit_direct(job, ring, &f);
|
|
if (r)
|
|
goto err;
|
|
|
|
if (fence)
|
|
*fence = dma_fence_get(f);
|
|
dma_fence_put(f);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
amdgpu_job_free(job);
|
|
return r;
|
|
}
|
|
|
|
int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
|
|
{
|
|
struct dma_fence *fence = NULL;
|
|
long r;
|
|
|
|
r = amdgpu_vcn_enc_get_create_msg(ring, 1, NULL);
|
|
if (r)
|
|
goto error;
|
|
|
|
r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &fence);
|
|
if (r)
|
|
goto error;
|
|
|
|
r = dma_fence_wait_timeout(fence, false, timeout);
|
|
if (r == 0)
|
|
r = -ETIMEDOUT;
|
|
else if (r > 0)
|
|
r = 0;
|
|
|
|
error:
|
|
dma_fence_put(fence);
|
|
return r;
|
|
}
|
|
|
|
int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
|
|
{
|
|
struct amdgpu_device *adev = ring->adev;
|
|
uint32_t tmp = 0;
|
|
unsigned i;
|
|
int r;
|
|
|
|
WREG32(adev->vcn.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD);
|
|
r = amdgpu_ring_alloc(ring, 3);
|
|
if (r)
|
|
return r;
|
|
|
|
amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.jpeg_pitch, 0));
|
|
amdgpu_ring_write(ring, 0xDEADBEEF);
|
|
amdgpu_ring_commit(ring);
|
|
|
|
for (i = 0; i < adev->usec_timeout; i++) {
|
|
tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch);
|
|
if (tmp == 0xDEADBEEF)
|
|
break;
|
|
udelay(1);
|
|
}
|
|
|
|
if (i >= adev->usec_timeout)
|
|
r = -ETIMEDOUT;
|
|
|
|
return r;
|
|
}
|
|
|
|
static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle,
|
|
struct dma_fence **fence)
|
|
{
|
|
struct amdgpu_device *adev = ring->adev;
|
|
struct amdgpu_job *job;
|
|
struct amdgpu_ib *ib;
|
|
struct dma_fence *f = NULL;
|
|
const unsigned ib_size_dw = 16;
|
|
int i, r;
|
|
|
|
r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
|
|
if (r)
|
|
return r;
|
|
|
|
ib = &job->ibs[0];
|
|
|
|
ib->ptr[0] = PACKETJ(adev->vcn.internal.jpeg_pitch, 0, 0, PACKETJ_TYPE0);
|
|
ib->ptr[1] = 0xDEADBEEF;
|
|
for (i = 2; i < 16; i += 2) {
|
|
ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
|
|
ib->ptr[i+1] = 0;
|
|
}
|
|
ib->length_dw = 16;
|
|
|
|
r = amdgpu_job_submit_direct(job, ring, &f);
|
|
if (r)
|
|
goto err;
|
|
|
|
if (fence)
|
|
*fence = dma_fence_get(f);
|
|
dma_fence_put(f);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
amdgpu_job_free(job);
|
|
return r;
|
|
}
|
|
|
|
int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout)
|
|
{
|
|
struct amdgpu_device *adev = ring->adev;
|
|
uint32_t tmp = 0;
|
|
unsigned i;
|
|
struct dma_fence *fence = NULL;
|
|
long r = 0;
|
|
|
|
r = amdgpu_vcn_jpeg_set_reg(ring, 1, &fence);
|
|
if (r)
|
|
goto error;
|
|
|
|
r = dma_fence_wait_timeout(fence, false, timeout);
|
|
if (r == 0) {
|
|
r = -ETIMEDOUT;
|
|
goto error;
|
|
} else if (r < 0) {
|
|
goto error;
|
|
} else {
|
|
r = 0;
|
|
}
|
|
|
|
for (i = 0; i < adev->usec_timeout; i++) {
|
|
tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch);
|
|
if (tmp == 0xDEADBEEF)
|
|
break;
|
|
udelay(1);
|
|
}
|
|
|
|
if (i >= adev->usec_timeout)
|
|
r = -ETIMEDOUT;
|
|
|
|
dma_fence_put(fence);
|
|
error:
|
|
return r;
|
|
}
|