forked from Minki/linux
17b27478cc
Current version of the driver does not support HDMI features not present in DVI standard. Therefore DVI mode is used to keep compatibility with DVI devices. Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
146 lines
5.2 KiB
C
146 lines
5.2 KiB
C
/* linux/arch/arm/mach-exynos4/include/mach/regs-hdmi.h
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* HDMI register header file for Samsung TVOUT driver
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef SAMSUNG_REGS_HDMI_H
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#define SAMSUNG_REGS_HDMI_H
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/*
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* Register part
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*/
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#define HDMI_CTRL_BASE(x) ((x) + 0x00000000)
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#define HDMI_CORE_BASE(x) ((x) + 0x00010000)
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#define HDMI_TG_BASE(x) ((x) + 0x00050000)
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/* Control registers */
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#define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000)
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#define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004)
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#define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C)
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#define HDMI_PHY_RSTOUT HDMI_CTRL_BASE(0x0014)
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#define HDMI_PHY_VPLL HDMI_CTRL_BASE(0x0018)
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#define HDMI_PHY_CMU HDMI_CTRL_BASE(0x001C)
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#define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0020)
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/* Core registers */
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#define HDMI_CON_0 HDMI_CORE_BASE(0x0000)
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#define HDMI_CON_1 HDMI_CORE_BASE(0x0004)
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#define HDMI_CON_2 HDMI_CORE_BASE(0x0008)
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#define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010)
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#define HDMI_PHY_STATUS HDMI_CORE_BASE(0x0014)
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#define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020)
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#define HDMI_HPD HDMI_CORE_BASE(0x0030)
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#define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040)
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#define HDMI_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050)
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#define HDMI_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054)
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#define HDMI_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058)
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#define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0)
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#define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4)
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#define HDMI_V_BLANK_0 HDMI_CORE_BASE(0x00B0)
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#define HDMI_V_BLANK_1 HDMI_CORE_BASE(0x00B4)
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#define HDMI_V_BLANK_2 HDMI_CORE_BASE(0x00B8)
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#define HDMI_H_V_LINE_0 HDMI_CORE_BASE(0x00C0)
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#define HDMI_H_V_LINE_1 HDMI_CORE_BASE(0x00C4)
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#define HDMI_H_V_LINE_2 HDMI_CORE_BASE(0x00C8)
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#define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4)
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#define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8)
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#define HDMI_V_BLANK_F_0 HDMI_CORE_BASE(0x0110)
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#define HDMI_V_BLANK_F_1 HDMI_CORE_BASE(0x0114)
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#define HDMI_V_BLANK_F_2 HDMI_CORE_BASE(0x0118)
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#define HDMI_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120)
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#define HDMI_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124)
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#define HDMI_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128)
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#define HDMI_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130)
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#define HDMI_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134)
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#define HDMI_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138)
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#define HDMI_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140)
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#define HDMI_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144)
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#define HDMI_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148)
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#define HDMI_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150)
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#define HDMI_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154)
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#define HDMI_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158)
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#define HDMI_AVI_CON HDMI_CORE_BASE(0x0300)
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#define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n))
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#define HDMI_DC_CONTROL HDMI_CORE_BASE(0x05C0)
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#define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4)
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#define HDMI_HPD_GEN HDMI_CORE_BASE(0x05C8)
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/* Timing generator registers */
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#define HDMI_TG_CMD HDMI_TG_BASE(0x0000)
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#define HDMI_TG_H_FSZ_L HDMI_TG_BASE(0x0018)
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#define HDMI_TG_H_FSZ_H HDMI_TG_BASE(0x001C)
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#define HDMI_TG_HACT_ST_L HDMI_TG_BASE(0x0020)
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#define HDMI_TG_HACT_ST_H HDMI_TG_BASE(0x0024)
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#define HDMI_TG_HACT_SZ_L HDMI_TG_BASE(0x0028)
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#define HDMI_TG_HACT_SZ_H HDMI_TG_BASE(0x002C)
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#define HDMI_TG_V_FSZ_L HDMI_TG_BASE(0x0030)
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#define HDMI_TG_V_FSZ_H HDMI_TG_BASE(0x0034)
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#define HDMI_TG_VSYNC_L HDMI_TG_BASE(0x0038)
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#define HDMI_TG_VSYNC_H HDMI_TG_BASE(0x003C)
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#define HDMI_TG_VSYNC2_L HDMI_TG_BASE(0x0040)
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#define HDMI_TG_VSYNC2_H HDMI_TG_BASE(0x0044)
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#define HDMI_TG_VACT_ST_L HDMI_TG_BASE(0x0048)
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#define HDMI_TG_VACT_ST_H HDMI_TG_BASE(0x004C)
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#define HDMI_TG_VACT_SZ_L HDMI_TG_BASE(0x0050)
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#define HDMI_TG_VACT_SZ_H HDMI_TG_BASE(0x0054)
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#define HDMI_TG_FIELD_CHG_L HDMI_TG_BASE(0x0058)
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#define HDMI_TG_FIELD_CHG_H HDMI_TG_BASE(0x005C)
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#define HDMI_TG_VACT_ST2_L HDMI_TG_BASE(0x0060)
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#define HDMI_TG_VACT_ST2_H HDMI_TG_BASE(0x0064)
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#define HDMI_TG_VSYNC_TOP_HDMI_L HDMI_TG_BASE(0x0078)
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#define HDMI_TG_VSYNC_TOP_HDMI_H HDMI_TG_BASE(0x007C)
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#define HDMI_TG_VSYNC_BOT_HDMI_L HDMI_TG_BASE(0x0080)
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#define HDMI_TG_VSYNC_BOT_HDMI_H HDMI_TG_BASE(0x0084)
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#define HDMI_TG_FIELD_TOP_HDMI_L HDMI_TG_BASE(0x0088)
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#define HDMI_TG_FIELD_TOP_HDMI_H HDMI_TG_BASE(0x008C)
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#define HDMI_TG_FIELD_BOT_HDMI_L HDMI_TG_BASE(0x0090)
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#define HDMI_TG_FIELD_BOT_HDMI_H HDMI_TG_BASE(0x0094)
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/*
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* Bit definition part
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*/
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/* HDMI_INTC_CON */
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#define HDMI_INTC_EN_GLOBAL (1 << 6)
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#define HDMI_INTC_EN_HPD_PLUG (1 << 3)
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#define HDMI_INTC_EN_HPD_UNPLUG (1 << 2)
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/* HDMI_INTC_FLAG */
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#define HDMI_INTC_FLAG_HPD_PLUG (1 << 3)
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#define HDMI_INTC_FLAG_HPD_UNPLUG (1 << 2)
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/* HDMI_PHY_RSTOUT */
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#define HDMI_PHY_SW_RSTOUT (1 << 0)
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/* HDMI_CORE_RSTOUT */
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#define HDMI_CORE_SW_RSTOUT (1 << 0)
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/* HDMI_CON_0 */
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#define HDMI_BLUE_SCR_EN (1 << 5)
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#define HDMI_EN (1 << 0)
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/* HDMI_CON_2 */
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#define HDMI_DVI_PERAMBLE_EN (1 << 5)
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#define HDMI_DVI_BAND_EN (1 << 1)
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/* HDMI_PHY_STATUS */
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#define HDMI_PHY_STATUS_READY (1 << 0)
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/* HDMI_MODE_SEL */
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#define HDMI_MODE_HDMI_EN (1 << 1)
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#define HDMI_MODE_DVI_EN (1 << 0)
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#define HDMI_MODE_MASK (3 << 0)
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/* HDMI_TG_CMD */
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#define HDMI_TG_EN (1 << 0)
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#endif /* SAMSUNG_REGS_HDMI_H */
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