forked from Minki/linux
d506735b1a
The B (segment size) field in the RB operand for the tlbie instruction is two bits, which we get from the top two bits of the first doubleword of the HPT entry to be invalidated. These bits go in bits 8 and 9 of the RB operand (bits 54 and 55 in IBM bit numbering). The compute_tlbie_rb() function gets these bits as v >> (62 - 8), which is not correct as it will bring in the top 10 bits, not just the top two. These extra bits could corrupt the AP, AVAL and L fields in the RB value. To fix this we shift right 62 bits and then shift left 8 bits, so we only get the two bits of the B field. The first doubleword of the HPT entry is under the control of the guest kernel. In fact, Linux guests will always put zeroes in bits 54 -- 61 (IBM bits 2 -- 9), but we should not rely on guests doing this. Signed-off-by: Paul Mackerras <paulus@samba.org> Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
429 lines
11 KiB
C
429 lines
11 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright SUSE Linux Products GmbH 2010
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*
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* Authors: Alexander Graf <agraf@suse.de>
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*/
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#ifndef __ASM_KVM_BOOK3S_64_H__
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#define __ASM_KVM_BOOK3S_64_H__
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#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
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static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu)
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{
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preempt_disable();
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return &get_paca()->shadow_vcpu;
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}
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static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
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{
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preempt_enable();
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}
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#endif
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#define SPAPR_TCE_SHIFT 12
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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#define KVM_DEFAULT_HPT_ORDER 24 /* 16MB HPT by default */
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extern unsigned long kvm_rma_pages;
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#endif
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#define VRMA_VSID 0x1ffffffUL /* 1TB VSID reserved for VRMA */
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/*
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* We use a lock bit in HPTE dword 0 to synchronize updates and
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* accesses to each HPTE, and another bit to indicate non-present
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* HPTEs.
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*/
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#define HPTE_V_HVLOCK 0x40UL
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#define HPTE_V_ABSENT 0x20UL
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/*
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* We use this bit in the guest_rpte field of the revmap entry
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* to indicate a modified HPTE.
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*/
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#define HPTE_GR_MODIFIED (1ul << 62)
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/* These bits are reserved in the guest view of the HPTE */
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#define HPTE_GR_RESERVED HPTE_GR_MODIFIED
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static inline long try_lock_hpte(__be64 *hpte, unsigned long bits)
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{
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unsigned long tmp, old;
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__be64 be_lockbit, be_bits;
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/*
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* We load/store in native endian, but the HTAB is in big endian. If
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* we byte swap all data we apply on the PTE we're implicitly correct
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* again.
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*/
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be_lockbit = cpu_to_be64(HPTE_V_HVLOCK);
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be_bits = cpu_to_be64(bits);
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asm volatile(" ldarx %0,0,%2\n"
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" and. %1,%0,%3\n"
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" bne 2f\n"
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" or %0,%0,%4\n"
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" stdcx. %0,0,%2\n"
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" beq+ 2f\n"
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" mr %1,%3\n"
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"2: isync"
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: "=&r" (tmp), "=&r" (old)
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: "r" (hpte), "r" (be_bits), "r" (be_lockbit)
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: "cc", "memory");
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return old == 0;
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}
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static inline int __hpte_actual_psize(unsigned int lp, int psize)
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{
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int i, shift;
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unsigned int mask;
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/* start from 1 ignoring MMU_PAGE_4K */
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for (i = 1; i < MMU_PAGE_COUNT; i++) {
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/* invalid penc */
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if (mmu_psize_defs[psize].penc[i] == -1)
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continue;
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/*
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* encoding bits per actual page size
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* PTE LP actual page size
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* rrrr rrrz >=8KB
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* rrrr rrzz >=16KB
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* rrrr rzzz >=32KB
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* rrrr zzzz >=64KB
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* .......
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*/
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shift = mmu_psize_defs[i].shift - LP_SHIFT;
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if (shift > LP_BITS)
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shift = LP_BITS;
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mask = (1 << shift) - 1;
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if ((lp & mask) == mmu_psize_defs[psize].penc[i])
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return i;
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}
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return -1;
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}
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static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
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unsigned long pte_index)
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{
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int b_psize = MMU_PAGE_4K, a_psize = MMU_PAGE_4K;
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unsigned int penc;
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unsigned long rb = 0, va_low, sllp;
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unsigned int lp = (r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
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if (v & HPTE_V_LARGE) {
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for (b_psize = 0; b_psize < MMU_PAGE_COUNT; b_psize++) {
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/* valid entries have a shift value */
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if (!mmu_psize_defs[b_psize].shift)
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continue;
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a_psize = __hpte_actual_psize(lp, b_psize);
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if (a_psize != -1)
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break;
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}
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}
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/*
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* Ignore the top 14 bits of va
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* v have top two bits covering segment size, hence move
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* by 16 bits, Also clear the lower HPTE_V_AVPN_SHIFT (7) bits.
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* AVA field in v also have the lower 23 bits ignored.
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* For base page size 4K we need 14 .. 65 bits (so need to
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* collect extra 11 bits)
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* For others we need 14..14+i
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*/
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/* This covers 14..54 bits of va*/
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rb = (v & ~0x7fUL) << 16; /* AVA field */
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rb |= (v >> HPTE_V_SSIZE_SHIFT) << 8; /* B field */
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/*
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* AVA in v had cleared lower 23 bits. We need to derive
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* that from pteg index
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*/
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va_low = pte_index >> 3;
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if (v & HPTE_V_SECONDARY)
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va_low = ~va_low;
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/*
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* get the vpn bits from va_low using reverse of hashing.
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* In v we have va with 23 bits dropped and then left shifted
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* HPTE_V_AVPN_SHIFT (7) bits. Now to find vsid we need
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* right shift it with (SID_SHIFT - (23 - 7))
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*/
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if (!(v & HPTE_V_1TB_SEG))
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va_low ^= v >> (SID_SHIFT - 16);
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else
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va_low ^= v >> (SID_SHIFT_1T - 16);
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va_low &= 0x7ff;
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switch (b_psize) {
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case MMU_PAGE_4K:
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sllp = ((mmu_psize_defs[a_psize].sllp & SLB_VSID_L) >> 6) |
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((mmu_psize_defs[a_psize].sllp & SLB_VSID_LP) >> 4);
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rb |= sllp << 5; /* AP field */
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rb |= (va_low & 0x7ff) << 12; /* remaining 11 bits of AVA */
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break;
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default:
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{
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int aval_shift;
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/*
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* remaining bits of AVA/LP fields
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* Also contain the rr bits of LP
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*/
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rb |= (va_low << mmu_psize_defs[b_psize].shift) & 0x7ff000;
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/*
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* Now clear not needed LP bits based on actual psize
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*/
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rb &= ~((1ul << mmu_psize_defs[a_psize].shift) - 1);
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/*
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* AVAL field 58..77 - base_page_shift bits of va
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* we have space for 58..64 bits, Missing bits should
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* be zero filled. +1 is to take care of L bit shift
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*/
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aval_shift = 64 - (77 - mmu_psize_defs[b_psize].shift) + 1;
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rb |= ((va_low << aval_shift) & 0xfe);
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rb |= 1; /* L field */
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penc = mmu_psize_defs[b_psize].penc[a_psize];
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rb |= penc << 12; /* LP field */
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break;
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}
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}
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rb |= (v >> 54) & 0x300; /* B field */
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return rb;
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}
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static inline unsigned long __hpte_page_size(unsigned long h, unsigned long l,
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bool is_base_size)
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{
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int size, a_psize;
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/* Look at the 8 bit LP value */
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unsigned int lp = (l >> LP_SHIFT) & ((1 << LP_BITS) - 1);
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/* only handle 4k, 64k and 16M pages for now */
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if (!(h & HPTE_V_LARGE))
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return 1ul << 12;
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else {
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for (size = 0; size < MMU_PAGE_COUNT; size++) {
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/* valid entries have a shift value */
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if (!mmu_psize_defs[size].shift)
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continue;
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a_psize = __hpte_actual_psize(lp, size);
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if (a_psize != -1) {
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if (is_base_size)
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return 1ul << mmu_psize_defs[size].shift;
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return 1ul << mmu_psize_defs[a_psize].shift;
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}
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}
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}
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return 0;
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}
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static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
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{
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return __hpte_page_size(h, l, 0);
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}
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static inline unsigned long hpte_base_page_size(unsigned long h, unsigned long l)
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{
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return __hpte_page_size(h, l, 1);
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}
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static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
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{
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return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
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}
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static inline int hpte_is_writable(unsigned long ptel)
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{
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unsigned long pp = ptel & (HPTE_R_PP0 | HPTE_R_PP);
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return pp != PP_RXRX && pp != PP_RXXX;
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}
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static inline unsigned long hpte_make_readonly(unsigned long ptel)
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{
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if ((ptel & HPTE_R_PP0) || (ptel & HPTE_R_PP) == PP_RWXX)
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ptel = (ptel & ~HPTE_R_PP) | PP_RXXX;
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else
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ptel |= PP_RXRX;
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return ptel;
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}
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static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type)
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{
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unsigned int wimg = ptel & HPTE_R_WIMG;
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/* Handle SAO */
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if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) &&
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cpu_has_feature(CPU_FTR_ARCH_206))
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wimg = HPTE_R_M;
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if (!io_type)
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return wimg == HPTE_R_M;
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return (wimg & (HPTE_R_W | HPTE_R_I)) == io_type;
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}
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/*
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* If it's present and writable, atomically set dirty and referenced bits and
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* return the PTE, otherwise return 0. If we find a transparent hugepage
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* and if it is marked splitting we return 0;
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*/
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static inline pte_t kvmppc_read_update_linux_pte(pte_t *ptep, int writing,
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unsigned int hugepage)
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{
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pte_t old_pte, new_pte = __pte(0);
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while (1) {
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old_pte = pte_val(*ptep);
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/*
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* wait until _PAGE_BUSY is clear then set it atomically
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*/
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if (unlikely(old_pte & _PAGE_BUSY)) {
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cpu_relax();
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continue;
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}
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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/* If hugepage and is trans splitting return None */
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if (unlikely(hugepage &&
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pmd_trans_splitting(pte_pmd(old_pte))))
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return __pte(0);
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#endif
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/* If pte is not present return None */
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if (unlikely(!(old_pte & _PAGE_PRESENT)))
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return __pte(0);
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new_pte = pte_mkyoung(old_pte);
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if (writing && pte_write(old_pte))
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new_pte = pte_mkdirty(new_pte);
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if (old_pte == __cmpxchg_u64((unsigned long *)ptep, old_pte,
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new_pte))
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break;
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}
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return new_pte;
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}
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/* Return HPTE cache control bits corresponding to Linux pte bits */
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static inline unsigned long hpte_cache_bits(unsigned long pte_val)
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{
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#if _PAGE_NO_CACHE == HPTE_R_I && _PAGE_WRITETHRU == HPTE_R_W
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return pte_val & (HPTE_R_W | HPTE_R_I);
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#else
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return ((pte_val & _PAGE_NO_CACHE) ? HPTE_R_I : 0) +
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((pte_val & _PAGE_WRITETHRU) ? HPTE_R_W : 0);
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#endif
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}
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static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
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{
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if (key)
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return PP_RWRX <= pp && pp <= PP_RXRX;
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return 1;
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}
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static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
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{
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if (key)
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return pp == PP_RWRW;
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return pp <= PP_RWRW;
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}
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static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr)
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{
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unsigned long skey;
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skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) |
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((hpte_r & HPTE_R_KEY_LO) >> 9);
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return (amr >> (62 - 2 * skey)) & 3;
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}
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static inline void lock_rmap(unsigned long *rmap)
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{
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do {
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while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap))
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cpu_relax();
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} while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap));
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}
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static inline void unlock_rmap(unsigned long *rmap)
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{
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__clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap);
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}
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static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
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unsigned long pagesize)
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{
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unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;
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if (pagesize <= PAGE_SIZE)
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return 1;
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return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
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}
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/*
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* This works for 4k, 64k and 16M pages on POWER7,
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* and 4k and 16M pages on PPC970.
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*/
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static inline unsigned long slb_pgsize_encoding(unsigned long psize)
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{
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unsigned long senc = 0;
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if (psize > 0x1000) {
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senc = SLB_VSID_L;
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if (psize == 0x10000)
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senc |= SLB_VSID_LP_01;
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}
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return senc;
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}
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static inline int is_vrma_hpte(unsigned long hpte_v)
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{
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return (hpte_v & ~0xffffffUL) ==
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(HPTE_V_1TB_SEG | (VRMA_VSID << (40 - 16)));
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}
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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/*
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* Note modification of an HPTE; set the HPTE modified bit
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* if anyone is interested.
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*/
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static inline void note_hpte_modification(struct kvm *kvm,
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struct revmap_entry *rev)
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{
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if (atomic_read(&kvm->arch.hpte_mod_interest))
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rev->guest_rpte |= HPTE_GR_MODIFIED;
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}
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/*
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* Like kvm_memslots(), but for use in real mode when we can't do
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* any RCU stuff (since the secondary threads are offline from the
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* kernel's point of view), and we can't print anything.
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* Thus we use rcu_dereference_raw() rather than rcu_dereference_check().
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*/
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static inline struct kvm_memslots *kvm_memslots_raw(struct kvm *kvm)
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{
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return rcu_dereference_raw_notrace(kvm->memslots);
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}
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#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
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#endif /* __ASM_KVM_BOOK3S_64_H__ */
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