forked from Minki/linux
d4fdc08e25
Not working reliably yet. Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1740 lines
50 KiB
C
1740 lines
50 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include "atom-types.h"
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#include "atombios.h"
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#include "processpptables.h"
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#include "pp_debug.h"
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#include "cgs_common.h"
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#include "smu/smu_8_0_d.h"
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#include "smu8_fusion.h"
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#include "smu/smu_8_0_sh_mask.h"
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#include "smumgr.h"
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#include "hwmgr.h"
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#include "hardwaremanager.h"
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#include "cz_ppsmc.h"
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#include "cz_hwmgr.h"
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#include "power_state.h"
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#include "cz_clockpowergating.h"
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#include "pp_debug.h"
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#define ixSMUSVI_NB_CURRENTVID 0xD8230044
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#define CURRENT_NB_VID_MASK 0xff000000
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#define CURRENT_NB_VID__SHIFT 24
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#define ixSMUSVI_GFX_CURRENTVID 0xD8230048
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#define CURRENT_GFX_VID_MASK 0xff000000
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#define CURRENT_GFX_VID__SHIFT 24
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static const unsigned long PhwCz_Magic = (unsigned long) PHM_Cz_Magic;
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static struct cz_power_state *cast_PhwCzPowerState(struct pp_hw_power_state *hw_ps)
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{
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if (PhwCz_Magic != hw_ps->magic)
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return NULL;
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return (struct cz_power_state *)hw_ps;
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}
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static const struct cz_power_state *cast_const_PhwCzPowerState(
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const struct pp_hw_power_state *hw_ps)
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{
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if (PhwCz_Magic != hw_ps->magic)
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return NULL;
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return (struct cz_power_state *)hw_ps;
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}
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uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
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uint32_t clock, uint32_t msg)
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{
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int i = 0;
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struct phm_vce_clock_voltage_dependency_table *ptable =
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hwmgr->dyn_state.vce_clock_voltage_dependency_table;
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switch (msg) {
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case PPSMC_MSG_SetEclkSoftMin:
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case PPSMC_MSG_SetEclkHardMin:
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for (i = 0; i < (int)ptable->count; i++) {
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if (clock <= ptable->entries[i].ecclk)
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break;
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}
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break;
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case PPSMC_MSG_SetEclkSoftMax:
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case PPSMC_MSG_SetEclkHardMax:
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for (i = ptable->count - 1; i >= 0; i--) {
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if (clock >= ptable->entries[i].ecclk)
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break;
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}
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break;
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default:
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break;
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}
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return i;
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}
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static uint32_t cz_get_sclk_level(struct pp_hwmgr *hwmgr,
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uint32_t clock, uint32_t msg)
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{
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int i = 0;
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struct phm_clock_voltage_dependency_table *table =
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hwmgr->dyn_state.vddc_dependency_on_sclk;
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switch (msg) {
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case PPSMC_MSG_SetSclkSoftMin:
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case PPSMC_MSG_SetSclkHardMin:
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for (i = 0; i < (int)table->count; i++) {
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if (clock <= table->entries[i].clk)
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break;
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}
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break;
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case PPSMC_MSG_SetSclkSoftMax:
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case PPSMC_MSG_SetSclkHardMax:
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for (i = table->count - 1; i >= 0; i--) {
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if (clock >= table->entries[i].clk)
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break;
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}
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break;
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default:
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break;
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}
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return i;
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}
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static uint32_t cz_get_uvd_level(struct pp_hwmgr *hwmgr,
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uint32_t clock, uint32_t msg)
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{
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int i = 0;
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struct phm_uvd_clock_voltage_dependency_table *ptable =
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hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
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switch (msg) {
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case PPSMC_MSG_SetUvdSoftMin:
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case PPSMC_MSG_SetUvdHardMin:
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for (i = 0; i < (int)ptable->count; i++) {
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if (clock <= ptable->entries[i].vclk)
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break;
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}
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break;
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case PPSMC_MSG_SetUvdSoftMax:
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case PPSMC_MSG_SetUvdHardMax:
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for (i = ptable->count - 1; i >= 0; i--) {
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if (clock >= ptable->entries[i].vclk)
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break;
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}
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break;
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default:
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break;
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}
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return i;
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}
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static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
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{
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struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
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if (cz_hwmgr->max_sclk_level == 0) {
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smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel);
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cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1;
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}
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return cz_hwmgr->max_sclk_level;
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}
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static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
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{
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struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
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uint32_t i;
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cz_hwmgr->gfx_ramp_step = 256*25/100;
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cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
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for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
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cz_hwmgr->activity_target[i] = CZ_AT_DFLT;
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cz_hwmgr->mgcg_cgtt_local0 = 0x00000000;
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cz_hwmgr->mgcg_cgtt_local1 = 0x00000000;
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cz_hwmgr->clock_slow_down_freq = 25000;
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cz_hwmgr->skip_clock_slow_down = 1;
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cz_hwmgr->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */
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cz_hwmgr->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */
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cz_hwmgr->voting_rights_clients = 0x00C00033;
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cz_hwmgr->static_screen_threshold = 8;
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cz_hwmgr->ddi_power_gating_disabled = 0;
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cz_hwmgr->bapm_enabled = 1;
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cz_hwmgr->voltage_drop_threshold = 0;
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cz_hwmgr->gfx_power_gating_threshold = 500;
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cz_hwmgr->vce_slow_sclk_threshold = 20000;
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cz_hwmgr->dce_slow_sclk_threshold = 30000;
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cz_hwmgr->disable_driver_thermal_policy = 1;
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cz_hwmgr->disable_nb_ps3_in_battery = 0;
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phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_ABM);
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_NonABMSupportInPPLib);
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_SclkDeepSleep);
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phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_DynamicM3Arbiter);
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cz_hwmgr->override_dynamic_mgpg = 1;
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_DynamicPatchPowerState);
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cz_hwmgr->thermal_auto_throttling_treshold = 0;
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cz_hwmgr->tdr_clock = 0;
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cz_hwmgr->disable_gfx_power_gating_in_uvd = 0;
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_DynamicUVDState);
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cz_hwmgr->cc6_settings.cpu_cc6_disable = false;
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cz_hwmgr->cc6_settings.cpu_pstate_disable = false;
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cz_hwmgr->cc6_settings.nb_pstate_switch_disable = false;
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cz_hwmgr->cc6_settings.cpu_pstate_separation_time = 0;
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_DisableVoltageIsland);
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phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_UVDPowerGating);
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return 0;
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}
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static uint32_t cz_convert_8Bit_index_to_voltage(
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struct pp_hwmgr *hwmgr, uint16_t voltage)
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{
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return 6200 - (voltage * 25);
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}
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static int cz_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
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struct phm_clock_and_voltage_limits *table)
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{
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struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
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struct cz_sys_info *sys_info = &cz_hwmgr->sys_info;
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struct phm_clock_voltage_dependency_table *dep_table =
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hwmgr->dyn_state.vddc_dependency_on_sclk;
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if (dep_table->count > 0) {
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table->sclk = dep_table->entries[dep_table->count-1].clk;
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table->vddc = cz_convert_8Bit_index_to_voltage(hwmgr,
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(uint16_t)dep_table->entries[dep_table->count-1].v);
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}
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table->mclk = sys_info->nbp_memory_clock[0];
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return 0;
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}
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static int cz_init_dynamic_state_adjustment_rule_settings(
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struct pp_hwmgr *hwmgr,
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ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table)
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{
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uint32_t table_size =
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sizeof(struct phm_clock_voltage_dependency_table) +
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(7 * sizeof(struct phm_clock_voltage_dependency_record));
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struct phm_clock_voltage_dependency_table *table_clk_vlt =
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kzalloc(table_size, GFP_KERNEL);
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if (NULL == table_clk_vlt) {
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printk(KERN_ERR "[ powerplay ] Can not allocate memory!\n");
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return -ENOMEM;
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}
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table_clk_vlt->count = 8;
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table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
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table_clk_vlt->entries[0].v = 0;
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table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
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table_clk_vlt->entries[1].v = 1;
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table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
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table_clk_vlt->entries[2].v = 2;
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table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
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table_clk_vlt->entries[3].v = 3;
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table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
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table_clk_vlt->entries[4].v = 4;
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table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
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table_clk_vlt->entries[5].v = 5;
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table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
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table_clk_vlt->entries[6].v = 6;
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table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
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table_clk_vlt->entries[7].v = 7;
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hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
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return 0;
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}
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static int cz_get_system_info_data(struct pp_hwmgr *hwmgr)
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{
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struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
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ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL;
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uint32_t i;
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int result = 0;
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uint8_t frev, crev;
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uint16_t size;
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info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *) cgs_atom_get_data_table(
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hwmgr->device,
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GetIndexIntoMasterTable(DATA, IntegratedSystemInfo),
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&size, &frev, &crev);
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if (crev != 9) {
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printk(KERN_ERR "[ powerplay ] Unsupported IGP table: %d %d\n", frev, crev);
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return -EINVAL;
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}
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if (info == NULL) {
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printk(KERN_ERR "[ powerplay ] Could not retrieve the Integrated System Info Table!\n");
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return -EINVAL;
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}
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cz_hwmgr->sys_info.bootup_uma_clock =
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le32_to_cpu(info->ulBootUpUMAClock);
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cz_hwmgr->sys_info.bootup_engine_clock =
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le32_to_cpu(info->ulBootUpEngineClock);
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cz_hwmgr->sys_info.dentist_vco_freq =
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le32_to_cpu(info->ulDentistVCOFreq);
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cz_hwmgr->sys_info.system_config =
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le32_to_cpu(info->ulSystemConfig);
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cz_hwmgr->sys_info.bootup_nb_voltage_index =
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le16_to_cpu(info->usBootUpNBVoltage);
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cz_hwmgr->sys_info.htc_hyst_lmt =
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(info->ucHtcHystLmt == 0) ? 5 : info->ucHtcHystLmt;
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cz_hwmgr->sys_info.htc_tmp_lmt =
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(info->ucHtcTmpLmt == 0) ? 203 : info->ucHtcTmpLmt;
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if (cz_hwmgr->sys_info.htc_tmp_lmt <=
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cz_hwmgr->sys_info.htc_hyst_lmt) {
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printk(KERN_ERR "[ powerplay ] The htcTmpLmt should be larger than htcHystLmt.\n");
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return -EINVAL;
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}
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cz_hwmgr->sys_info.nb_dpm_enable =
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cz_hwmgr->enable_nb_ps_policy &&
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(le32_to_cpu(info->ulSystemConfig) >> 3 & 0x1);
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for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
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if (i < CZ_NUM_NBPMEMORYCLOCK) {
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cz_hwmgr->sys_info.nbp_memory_clock[i] =
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le32_to_cpu(info->ulNbpStateMemclkFreq[i]);
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}
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cz_hwmgr->sys_info.nbp_n_clock[i] =
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le32_to_cpu(info->ulNbpStateNClkFreq[i]);
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}
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for (i = 0; i < MAX_DISPLAY_CLOCK_LEVEL; i++) {
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cz_hwmgr->sys_info.display_clock[i] =
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le32_to_cpu(info->sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
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}
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/* Here use 4 levels, make sure not exceed */
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for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
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cz_hwmgr->sys_info.nbp_voltage_index[i] =
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le16_to_cpu(info->usNBPStateVoltage[i]);
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}
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if (!cz_hwmgr->sys_info.nb_dpm_enable) {
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for (i = 1; i < CZ_NUM_NBPSTATES; i++) {
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if (i < CZ_NUM_NBPMEMORYCLOCK) {
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cz_hwmgr->sys_info.nbp_memory_clock[i] =
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cz_hwmgr->sys_info.nbp_memory_clock[0];
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}
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cz_hwmgr->sys_info.nbp_n_clock[i] =
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cz_hwmgr->sys_info.nbp_n_clock[0];
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cz_hwmgr->sys_info.nbp_voltage_index[i] =
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cz_hwmgr->sys_info.nbp_voltage_index[0];
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}
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}
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if (le32_to_cpu(info->ulGPUCapInfo) &
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SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) {
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_EnableDFSBypass);
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}
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cz_hwmgr->sys_info.uma_channel_number = info->ucUMAChannelNumber;
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cz_construct_max_power_limits_table (hwmgr,
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&hwmgr->dyn_state.max_clock_voltage_on_ac);
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cz_init_dynamic_state_adjustment_rule_settings(hwmgr,
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&info->sDISPCLK_Voltage[0]);
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return result;
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}
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static int cz_construct_boot_state(struct pp_hwmgr *hwmgr)
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{
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struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
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cz_hwmgr->boot_power_level.engineClock =
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cz_hwmgr->sys_info.bootup_engine_clock;
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cz_hwmgr->boot_power_level.vddcIndex =
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(uint8_t)cz_hwmgr->sys_info.bootup_nb_voltage_index;
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cz_hwmgr->boot_power_level.dsDividerIndex = 0;
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cz_hwmgr->boot_power_level.ssDividerIndex = 0;
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cz_hwmgr->boot_power_level.allowGnbSlow = 1;
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cz_hwmgr->boot_power_level.forceNBPstate = 0;
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cz_hwmgr->boot_power_level.hysteresis_up = 0;
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cz_hwmgr->boot_power_level.numSIMDToPowerDown = 0;
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cz_hwmgr->boot_power_level.display_wm = 0;
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cz_hwmgr->boot_power_level.vce_wm = 0;
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return 0;
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}
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static int cz_tf_reset_active_process_mask(struct pp_hwmgr *hwmgr, void *input,
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void *output, void *storage, int result)
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{
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return 0;
|
|
}
|
|
|
|
static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
|
|
void *output, void *storage, int result)
|
|
{
|
|
struct SMU8_Fusion_ClkTable *clock_table;
|
|
int ret;
|
|
uint32_t i;
|
|
void *table = NULL;
|
|
pp_atomctrl_clock_dividers_kong dividers;
|
|
|
|
struct phm_clock_voltage_dependency_table *vddc_table =
|
|
hwmgr->dyn_state.vddc_dependency_on_sclk;
|
|
struct phm_clock_voltage_dependency_table *vdd_gfx_table =
|
|
hwmgr->dyn_state.vdd_gfx_dependency_on_sclk;
|
|
struct phm_acp_clock_voltage_dependency_table *acp_table =
|
|
hwmgr->dyn_state.acp_clock_voltage_dependency_table;
|
|
struct phm_uvd_clock_voltage_dependency_table *uvd_table =
|
|
hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
|
|
struct phm_vce_clock_voltage_dependency_table *vce_table =
|
|
hwmgr->dyn_state.vce_clock_voltage_dependency_table;
|
|
|
|
if (!hwmgr->need_pp_table_upload)
|
|
return 0;
|
|
|
|
ret = smum_download_powerplay_table(hwmgr->smumgr, &table);
|
|
|
|
PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
|
|
"Fail to get clock table from SMU!", return -EINVAL;);
|
|
|
|
clock_table = (struct SMU8_Fusion_ClkTable *)table;
|
|
|
|
/* patch clock table */
|
|
PP_ASSERT_WITH_CODE((vddc_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
|
|
"Dependency table entry exceeds max limit!", return -EINVAL;);
|
|
PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
|
|
"Dependency table entry exceeds max limit!", return -EINVAL;);
|
|
PP_ASSERT_WITH_CODE((acp_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
|
|
"Dependency table entry exceeds max limit!", return -EINVAL;);
|
|
PP_ASSERT_WITH_CODE((uvd_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
|
|
"Dependency table entry exceeds max limit!", return -EINVAL;);
|
|
PP_ASSERT_WITH_CODE((vce_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
|
|
"Dependency table entry exceeds max limit!", return -EINVAL;);
|
|
|
|
for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
|
|
|
|
/* vddc_sclk */
|
|
clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
|
|
(i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
|
|
clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
|
|
(i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
|
|
|
|
atomctrl_get_engine_pll_dividers_kong(hwmgr,
|
|
clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
|
|
÷rs);
|
|
|
|
clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
|
|
(uint8_t)dividers.pll_post_divider;
|
|
|
|
/* vddgfx_sclk */
|
|
clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
|
|
(i < vdd_gfx_table->count) ? (uint8_t)vdd_gfx_table->entries[i].v : 0;
|
|
|
|
/* acp breakdown */
|
|
clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
|
|
(i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
|
|
clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
|
|
(i < acp_table->count) ? acp_table->entries[i].acpclk : 0;
|
|
|
|
atomctrl_get_engine_pll_dividers_kong(hwmgr,
|
|
clock_table->AclkBreakdownTable.ClkLevel[i].Frequency,
|
|
÷rs);
|
|
|
|
clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
|
|
(uint8_t)dividers.pll_post_divider;
|
|
|
|
|
|
/* uvd breakdown */
|
|
clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
|
|
(i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
|
|
clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
|
|
(i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
|
|
|
|
atomctrl_get_engine_pll_dividers_kong(hwmgr,
|
|
clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
|
|
÷rs);
|
|
|
|
clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
|
|
(uint8_t)dividers.pll_post_divider;
|
|
|
|
clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
|
|
(i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
|
|
clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
|
|
(i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
|
|
|
|
atomctrl_get_engine_pll_dividers_kong(hwmgr,
|
|
clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
|
|
÷rs);
|
|
|
|
clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
|
|
(uint8_t)dividers.pll_post_divider;
|
|
|
|
/* vce breakdown */
|
|
clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
|
|
(i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
|
|
clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
|
|
(i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
|
|
|
|
|
|
atomctrl_get_engine_pll_dividers_kong(hwmgr,
|
|
clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
|
|
÷rs);
|
|
|
|
clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
|
|
(uint8_t)dividers.pll_post_divider;
|
|
|
|
}
|
|
ret = smum_upload_powerplay_table(hwmgr->smumgr);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
|
|
void *output, void *storage, int result)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
struct phm_clock_voltage_dependency_table *table =
|
|
hwmgr->dyn_state.vddc_dependency_on_sclk;
|
|
unsigned long clock = 0, level;
|
|
|
|
if (NULL == table || table->count <= 0)
|
|
return -EINVAL;
|
|
|
|
cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
|
|
cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
|
|
|
|
level = cz_get_max_sclk_level(hwmgr) - 1;
|
|
|
|
if (level < table->count)
|
|
clock = table->entries[level].clk;
|
|
else
|
|
clock = table->entries[table->count - 1].clk;
|
|
|
|
cz_hwmgr->sclk_dpm.soft_max_clk = clock;
|
|
cz_hwmgr->sclk_dpm.hard_max_clk = clock;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
|
|
void *output, void *storage, int result)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
struct phm_uvd_clock_voltage_dependency_table *table =
|
|
hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
|
|
unsigned long clock = 0, level;
|
|
|
|
if (NULL == table || table->count <= 0)
|
|
return -EINVAL;
|
|
|
|
cz_hwmgr->uvd_dpm.soft_min_clk = 0;
|
|
cz_hwmgr->uvd_dpm.hard_min_clk = 0;
|
|
|
|
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel);
|
|
level = smum_get_argument(hwmgr->smumgr);
|
|
|
|
if (level < table->count)
|
|
clock = table->entries[level].vclk;
|
|
else
|
|
clock = table->entries[table->count - 1].vclk;
|
|
|
|
cz_hwmgr->uvd_dpm.soft_max_clk = clock;
|
|
cz_hwmgr->uvd_dpm.hard_max_clk = clock;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
|
|
void *output, void *storage, int result)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
struct phm_vce_clock_voltage_dependency_table *table =
|
|
hwmgr->dyn_state.vce_clock_voltage_dependency_table;
|
|
unsigned long clock = 0, level;
|
|
|
|
if (NULL == table || table->count <= 0)
|
|
return -EINVAL;
|
|
|
|
cz_hwmgr->vce_dpm.soft_min_clk = 0;
|
|
cz_hwmgr->vce_dpm.hard_min_clk = 0;
|
|
|
|
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel);
|
|
level = smum_get_argument(hwmgr->smumgr);
|
|
|
|
if (level < table->count)
|
|
clock = table->entries[level].ecclk;
|
|
else
|
|
clock = table->entries[table->count - 1].ecclk;
|
|
|
|
cz_hwmgr->vce_dpm.soft_max_clk = clock;
|
|
cz_hwmgr->vce_dpm.hard_max_clk = clock;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
|
|
void *output, void *storage, int result)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
struct phm_acp_clock_voltage_dependency_table *table =
|
|
hwmgr->dyn_state.acp_clock_voltage_dependency_table;
|
|
unsigned long clock = 0, level;
|
|
|
|
if (NULL == table || table->count <= 0)
|
|
return -EINVAL;
|
|
|
|
cz_hwmgr->acp_dpm.soft_min_clk = 0;
|
|
cz_hwmgr->acp_dpm.hard_min_clk = 0;
|
|
|
|
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel);
|
|
level = smum_get_argument(hwmgr->smumgr);
|
|
|
|
if (level < table->count)
|
|
clock = table->entries[level].acpclk;
|
|
else
|
|
clock = table->entries[table->count - 1].acpclk;
|
|
|
|
cz_hwmgr->acp_dpm.soft_max_clk = clock;
|
|
cz_hwmgr->acp_dpm.hard_max_clk = clock;
|
|
return 0;
|
|
}
|
|
|
|
static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
|
|
void *output, void *storage, int result)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
|
|
cz_hwmgr->uvd_power_gated = false;
|
|
cz_hwmgr->vce_power_gated = false;
|
|
cz_hwmgr->samu_power_gated = false;
|
|
cz_hwmgr->acp_power_gated = false;
|
|
cz_hwmgr->pgacpinit = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_tf_init_sclk_threshold(struct pp_hwmgr *hwmgr, void *input,
|
|
void *output, void *storage, int result)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
|
|
cz_hwmgr->low_sclk_interrupt_threshold = 0;
|
|
|
|
return 0;
|
|
}
|
|
static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
|
|
void *input, void *output,
|
|
void *storage, int result)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
struct phm_clock_voltage_dependency_table *table =
|
|
hwmgr->dyn_state.vddc_dependency_on_sclk;
|
|
|
|
unsigned long clock = 0;
|
|
unsigned long level;
|
|
unsigned long stable_pstate_sclk;
|
|
struct PP_Clocks clocks;
|
|
unsigned long percentage;
|
|
|
|
cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
|
|
level = cz_get_max_sclk_level(hwmgr) - 1;
|
|
|
|
if (level < table->count)
|
|
cz_hwmgr->sclk_dpm.soft_max_clk = table->entries[level].clk;
|
|
else
|
|
cz_hwmgr->sclk_dpm.soft_max_clk = table->entries[table->count - 1].clk;
|
|
|
|
/*PECI_GetMinClockSettings(pHwMgr->pPECI, &clocks);*/
|
|
clock = clocks.engineClock;
|
|
|
|
if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
|
|
cz_hwmgr->sclk_dpm.hard_min_clk = clock;
|
|
|
|
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_SetSclkHardMin,
|
|
cz_get_sclk_level(hwmgr,
|
|
cz_hwmgr->sclk_dpm.hard_min_clk,
|
|
PPSMC_MSG_SetSclkHardMin));
|
|
}
|
|
|
|
clock = cz_hwmgr->sclk_dpm.soft_min_clk;
|
|
|
|
/* update minimum clocks for Stable P-State feature */
|
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_StablePState)) {
|
|
percentage = 75;
|
|
/*Sclk - calculate sclk value based on percentage and find FLOOR sclk from VddcDependencyOnSCLK table */
|
|
stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk *
|
|
percentage) / 100;
|
|
|
|
if (clock < stable_pstate_sclk)
|
|
clock = stable_pstate_sclk;
|
|
} else {
|
|
if (clock < hwmgr->gfx_arbiter.sclk)
|
|
clock = hwmgr->gfx_arbiter.sclk;
|
|
}
|
|
|
|
if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
|
|
cz_hwmgr->sclk_dpm.soft_min_clk = clock;
|
|
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_SetSclkSoftMin,
|
|
cz_get_sclk_level(hwmgr,
|
|
cz_hwmgr->sclk_dpm.soft_min_clk,
|
|
PPSMC_MSG_SetSclkSoftMin));
|
|
}
|
|
|
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_StablePState) &&
|
|
cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
|
|
cz_hwmgr->sclk_dpm.soft_max_clk = clock;
|
|
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_SetSclkSoftMax,
|
|
cz_get_sclk_level(hwmgr,
|
|
cz_hwmgr->sclk_dpm.soft_max_clk,
|
|
PPSMC_MSG_SetSclkSoftMax));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
|
|
void *input, void *output,
|
|
void *storage, int result)
|
|
{
|
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_SclkDeepSleep)) {
|
|
uint32_t clks = hwmgr->display_config.min_core_set_clock_in_sr;
|
|
if (clks == 0)
|
|
clks = CZ_MIN_DEEP_SLEEP_SCLK;
|
|
|
|
PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
|
|
|
|
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_SetMinDeepSleepSclk,
|
|
clks);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_tf_set_watermark_threshold(struct pp_hwmgr *hwmgr,
|
|
void *input, void *output,
|
|
void *storage, int result)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr =
|
|
(struct cz_hwmgr *)(hwmgr->backend);
|
|
|
|
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_SetWatermarkFrequency,
|
|
cz_hwmgr->sclk_dpm.soft_max_clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_tf_set_enabled_levels(struct pp_hwmgr *hwmgr,
|
|
void *input, void *output,
|
|
void *storage, int result)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr,
|
|
void *input, void *output,
|
|
void *storage, int result)
|
|
{
|
|
int ret = 0;
|
|
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
unsigned long dpm_features = 0;
|
|
|
|
if (!cz_hwmgr->is_nb_dpm_enabled) {
|
|
PP_DBG_LOG("enabling ALL SMU features.\n");
|
|
dpm_features |= NB_DPM_MASK;
|
|
ret = smum_send_msg_to_smc_with_parameter(
|
|
hwmgr->smumgr,
|
|
PPSMC_MSG_EnableAllSmuFeatures,
|
|
dpm_features);
|
|
if (ret == 0)
|
|
cz_hwmgr->is_nb_dpm_enabled = true;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
|
|
{
|
|
struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
|
|
|
|
if (hw_data->is_nb_dpm_enabled) {
|
|
if (enable) {
|
|
PP_DBG_LOG("enable Low Memory PState.\n");
|
|
|
|
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_EnableLowMemoryPstate,
|
|
(lock ? 1 : 0));
|
|
} else {
|
|
PP_DBG_LOG("disable Low Memory PState.\n");
|
|
|
|
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_DisableLowMemoryPstate,
|
|
(lock ? 1 : 0));
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
|
|
void *input, void *output,
|
|
void *storage, int result)
|
|
{
|
|
bool disable_switch;
|
|
bool enable_low_mem_state;
|
|
struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
|
|
const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input;
|
|
const struct cz_power_state *pnew_state = cast_const_PhwCzPowerState(states->pnew_state);
|
|
|
|
if (hw_data->sys_info.nb_dpm_enable) {
|
|
disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;
|
|
enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;
|
|
|
|
if (pnew_state->action == FORCE_HIGH)
|
|
cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
|
|
else if(pnew_state->action == CANCEL_FORCE_HIGH)
|
|
cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
|
|
else
|
|
cz_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static struct phm_master_table_item cz_set_power_state_list[] = {
|
|
{NULL, cz_tf_update_sclk_limit},
|
|
{NULL, cz_tf_set_deep_sleep_sclk_threshold},
|
|
{NULL, cz_tf_set_watermark_threshold},
|
|
{NULL, cz_tf_set_enabled_levels},
|
|
{NULL, cz_tf_enable_nb_dpm},
|
|
{NULL, cz_tf_update_low_mem_pstate},
|
|
{NULL, NULL}
|
|
};
|
|
|
|
static struct phm_master_table_header cz_set_power_state_master = {
|
|
0,
|
|
PHM_MasterTableFlag_None,
|
|
cz_set_power_state_list
|
|
};
|
|
|
|
static struct phm_master_table_item cz_setup_asic_list[] = {
|
|
{NULL, cz_tf_reset_active_process_mask},
|
|
{NULL, cz_tf_upload_pptable_to_smu},
|
|
{NULL, cz_tf_init_sclk_limit},
|
|
{NULL, cz_tf_init_uvd_limit},
|
|
{NULL, cz_tf_init_vce_limit},
|
|
{NULL, cz_tf_init_acp_limit},
|
|
{NULL, cz_tf_init_power_gate_state},
|
|
{NULL, cz_tf_init_sclk_threshold},
|
|
{NULL, NULL}
|
|
};
|
|
|
|
static struct phm_master_table_header cz_setup_asic_master = {
|
|
0,
|
|
PHM_MasterTableFlag_None,
|
|
cz_setup_asic_list
|
|
};
|
|
|
|
static int cz_tf_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr,
|
|
void *input, void *output,
|
|
void *storage, int result)
|
|
{
|
|
struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
|
|
hw_data->disp_clk_bypass_pending = false;
|
|
hw_data->disp_clk_bypass = false;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_tf_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr,
|
|
void *input, void *output,
|
|
void *storage, int result)
|
|
{
|
|
struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
|
|
hw_data->is_nb_dpm_enabled = false;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
|
|
void *input, void *output,
|
|
void *storage, int result)
|
|
{
|
|
struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
|
|
|
|
hw_data->cc6_settings.cc6_setting_changed = false;
|
|
hw_data->cc6_settings.cpu_pstate_separation_time = 0;
|
|
hw_data->cc6_settings.cpu_cc6_disable = false;
|
|
hw_data->cc6_settings.cpu_pstate_disable = false;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct phm_master_table_item cz_power_down_asic_list[] = {
|
|
{NULL, cz_tf_power_up_display_clock_sys_pll},
|
|
{NULL, cz_tf_clear_nb_dpm_flag},
|
|
{NULL, cz_tf_reset_cc6_data},
|
|
{NULL, NULL}
|
|
};
|
|
|
|
static struct phm_master_table_header cz_power_down_asic_master = {
|
|
0,
|
|
PHM_MasterTableFlag_None,
|
|
cz_power_down_asic_list
|
|
};
|
|
|
|
static int cz_tf_program_voting_clients(struct pp_hwmgr *hwmgr, void *input,
|
|
void *output, void *storage, int result)
|
|
{
|
|
PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0,
|
|
PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
|
|
return 0;
|
|
}
|
|
|
|
static int cz_tf_start_dpm(struct pp_hwmgr *hwmgr, void *input, void *output,
|
|
void *storage, int result)
|
|
{
|
|
int res = 0xff;
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
unsigned long dpm_features = 0;
|
|
|
|
cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
|
|
dpm_features |= SCLK_DPM_MASK;
|
|
|
|
res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_EnableAllSmuFeatures,
|
|
dpm_features);
|
|
|
|
return res;
|
|
}
|
|
|
|
static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
|
|
void *output, void *storage, int result)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
|
|
cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
|
|
cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
|
|
|
|
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_SetSclkSoftMin,
|
|
cz_get_sclk_level(hwmgr,
|
|
cz_hwmgr->sclk_dpm.soft_min_clk,
|
|
PPSMC_MSG_SetSclkSoftMin));
|
|
|
|
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_SetSclkSoftMax,
|
|
cz_get_sclk_level(hwmgr,
|
|
cz_hwmgr->sclk_dpm.soft_max_clk,
|
|
PPSMC_MSG_SetSclkSoftMax));
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
|
|
void *output, void *storage, int result)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
|
|
cz_hwmgr->acp_boot_level = 0xff;
|
|
return 0;
|
|
}
|
|
|
|
static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
|
|
unsigned long check_feature)
|
|
{
|
|
int result;
|
|
unsigned long features;
|
|
|
|
result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetFeatureStatus, 0);
|
|
if (result == 0) {
|
|
features = smum_get_argument(hwmgr->smumgr);
|
|
if (features & check_feature)
|
|
return true;
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
static int cz_tf_check_for_dpm_disabled(struct pp_hwmgr *hwmgr, void *input,
|
|
void *output, void *storage, int result)
|
|
{
|
|
if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
|
|
return PP_Result_TableImmediateExit;
|
|
return 0;
|
|
}
|
|
|
|
static int cz_tf_enable_didt(struct pp_hwmgr *hwmgr, void *input,
|
|
void *output, void *storage, int result)
|
|
{
|
|
/* TO DO */
|
|
return 0;
|
|
}
|
|
|
|
static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr,
|
|
void *input, void *output,
|
|
void *storage, int result)
|
|
{
|
|
if (!cz_dpm_check_smu_features(hwmgr,
|
|
SMU_EnabledFeatureScoreboard_SclkDpmOn))
|
|
return PP_Result_TableImmediateExit;
|
|
return 0;
|
|
}
|
|
|
|
static struct phm_master_table_item cz_disable_dpm_list[] = {
|
|
{ NULL, cz_tf_check_for_dpm_enabled},
|
|
{NULL, NULL},
|
|
};
|
|
|
|
|
|
static struct phm_master_table_header cz_disable_dpm_master = {
|
|
0,
|
|
PHM_MasterTableFlag_None,
|
|
cz_disable_dpm_list
|
|
};
|
|
|
|
static struct phm_master_table_item cz_enable_dpm_list[] = {
|
|
{ NULL, cz_tf_check_for_dpm_disabled },
|
|
{ NULL, cz_tf_program_voting_clients },
|
|
{ NULL, cz_tf_start_dpm},
|
|
{ NULL, cz_tf_program_bootup_state},
|
|
{ NULL, cz_tf_enable_didt },
|
|
{ NULL, cz_tf_reset_acp_boot_level },
|
|
{NULL, NULL},
|
|
};
|
|
|
|
static struct phm_master_table_header cz_enable_dpm_master = {
|
|
0,
|
|
PHM_MasterTableFlag_None,
|
|
cz_enable_dpm_list
|
|
};
|
|
|
|
static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
|
|
struct pp_power_state *prequest_ps,
|
|
const struct pp_power_state *pcurrent_ps)
|
|
{
|
|
struct cz_power_state *cz_ps =
|
|
cast_PhwCzPowerState(&prequest_ps->hardware);
|
|
|
|
const struct cz_power_state *cz_current_ps =
|
|
cast_const_PhwCzPowerState(&pcurrent_ps->hardware);
|
|
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
struct PP_Clocks clocks;
|
|
bool force_high;
|
|
unsigned long num_of_active_displays = 4;
|
|
|
|
cz_ps->evclk = hwmgr->vce_arbiter.evclk;
|
|
cz_ps->ecclk = hwmgr->vce_arbiter.ecclk;
|
|
|
|
cz_ps->need_dfs_bypass = true;
|
|
|
|
cz_hwmgr->video_start = (hwmgr->uvd_arbiter.vclk != 0 || hwmgr->uvd_arbiter.dclk != 0 ||
|
|
hwmgr->vce_arbiter.evclk != 0 || hwmgr->vce_arbiter.ecclk != 0);
|
|
|
|
cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
|
|
|
|
/* to do PECI_GetMinClockSettings(pHwMgr->pPECI, &clocks); */
|
|
/* PECI_GetNumberOfActiveDisplays(pHwMgr->pPECI, &numOfActiveDisplays); */
|
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
|
|
clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
|
|
else
|
|
clocks.memoryClock = 0;
|
|
|
|
if (clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
|
|
clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
|
|
|
|
force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1])
|
|
|| (num_of_active_displays >= 3);
|
|
|
|
cz_ps->action = cz_current_ps->action;
|
|
|
|
if ((force_high == false) && (cz_ps->action == FORCE_HIGH))
|
|
cz_ps->action = CANCEL_FORCE_HIGH;
|
|
else if ((force_high == true) && (cz_ps->action != FORCE_HIGH))
|
|
cz_ps->action = FORCE_HIGH;
|
|
else
|
|
cz_ps->action = DO_NOTHING;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
|
|
{
|
|
int result = 0;
|
|
|
|
result = cz_initialize_dpm_defaults(hwmgr);
|
|
if (result != 0) {
|
|
printk(KERN_ERR "[ powerplay ] cz_initialize_dpm_defaults failed\n");
|
|
return result;
|
|
}
|
|
|
|
result = cz_get_system_info_data(hwmgr);
|
|
if (result != 0) {
|
|
printk(KERN_ERR "[ powerplay ] cz_get_system_info_data failed\n");
|
|
return result;
|
|
}
|
|
|
|
cz_construct_boot_state(hwmgr);
|
|
|
|
result = phm_construct_table(hwmgr, &cz_setup_asic_master,
|
|
&(hwmgr->setup_asic));
|
|
if (result != 0) {
|
|
printk(KERN_ERR "[ powerplay ] Fail to construct setup ASIC\n");
|
|
return result;
|
|
}
|
|
|
|
result = phm_construct_table(hwmgr, &cz_power_down_asic_master,
|
|
&(hwmgr->power_down_asic));
|
|
if (result != 0) {
|
|
printk(KERN_ERR "[ powerplay ] Fail to construct power down ASIC\n");
|
|
return result;
|
|
}
|
|
|
|
result = phm_construct_table(hwmgr, &cz_disable_dpm_master,
|
|
&(hwmgr->disable_dynamic_state_management));
|
|
if (result != 0) {
|
|
printk(KERN_ERR "[ powerplay ] Fail to disable_dynamic_state\n");
|
|
return result;
|
|
}
|
|
result = phm_construct_table(hwmgr, &cz_enable_dpm_master,
|
|
&(hwmgr->enable_dynamic_state_management));
|
|
if (result != 0) {
|
|
printk(KERN_ERR "[ powerplay ] Fail to enable_dynamic_state\n");
|
|
return result;
|
|
}
|
|
result = phm_construct_table(hwmgr, &cz_set_power_state_master,
|
|
&(hwmgr->set_power_state));
|
|
if (result != 0) {
|
|
printk(KERN_ERR "[ powerplay ] Fail to construct set_power_state\n");
|
|
return result;
|
|
}
|
|
|
|
result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings));
|
|
if (result != 0) {
|
|
printk(KERN_ERR "[ powerplay ] Fail to construct enable_clock_power_gatings\n");
|
|
return result;
|
|
}
|
|
return result;
|
|
}
|
|
|
|
static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
|
|
{
|
|
if (hwmgr != NULL || hwmgr->backend != NULL) {
|
|
kfree(hwmgr->backend);
|
|
kfree(hwmgr);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
|
|
if (cz_hwmgr->sclk_dpm.soft_min_clk !=
|
|
cz_hwmgr->sclk_dpm.soft_max_clk)
|
|
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_SetSclkSoftMin,
|
|
cz_get_sclk_level(hwmgr,
|
|
cz_hwmgr->sclk_dpm.soft_max_clk,
|
|
PPSMC_MSG_SetSclkSoftMin));
|
|
return 0;
|
|
}
|
|
|
|
int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
struct phm_clock_voltage_dependency_table *table =
|
|
hwmgr->dyn_state.vddc_dependency_on_sclk;
|
|
unsigned long clock = 0, level;
|
|
|
|
if (NULL == table || table->count <= 0)
|
|
return -EINVAL;
|
|
|
|
cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
|
|
cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
|
|
|
|
level = cz_get_max_sclk_level(hwmgr) - 1;
|
|
|
|
if (level < table->count)
|
|
clock = table->entries[level].clk;
|
|
else
|
|
clock = table->entries[table->count - 1].clk;
|
|
|
|
cz_hwmgr->sclk_dpm.soft_max_clk = clock;
|
|
cz_hwmgr->sclk_dpm.hard_max_clk = clock;
|
|
|
|
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_SetSclkSoftMin,
|
|
cz_get_sclk_level(hwmgr,
|
|
cz_hwmgr->sclk_dpm.soft_min_clk,
|
|
PPSMC_MSG_SetSclkSoftMin));
|
|
|
|
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_SetSclkSoftMax,
|
|
cz_get_sclk_level(hwmgr,
|
|
cz_hwmgr->sclk_dpm.soft_max_clk,
|
|
PPSMC_MSG_SetSclkSoftMax));
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
|
|
if (cz_hwmgr->sclk_dpm.soft_min_clk !=
|
|
cz_hwmgr->sclk_dpm.soft_max_clk) {
|
|
cz_hwmgr->sclk_dpm.soft_max_clk =
|
|
cz_hwmgr->sclk_dpm.soft_min_clk;
|
|
|
|
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_SetSclkSoftMax,
|
|
cz_get_sclk_level(hwmgr,
|
|
cz_hwmgr->sclk_dpm.soft_max_clk,
|
|
PPSMC_MSG_SetSclkSoftMax));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
|
|
enum amd_dpm_forced_level level)
|
|
{
|
|
int ret = 0;
|
|
|
|
switch (level) {
|
|
case AMD_DPM_FORCED_LEVEL_HIGH:
|
|
ret = cz_phm_force_dpm_highest(hwmgr);
|
|
if (ret)
|
|
return ret;
|
|
break;
|
|
case AMD_DPM_FORCED_LEVEL_LOW:
|
|
ret = cz_phm_force_dpm_lowest(hwmgr);
|
|
if (ret)
|
|
return ret;
|
|
break;
|
|
case AMD_DPM_FORCED_LEVEL_AUTO:
|
|
ret = cz_phm_unforce_dpm_levels(hwmgr);
|
|
if (ret)
|
|
return ret;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
hwmgr->dpm_level = level;
|
|
|
|
return ret;
|
|
}
|
|
|
|
int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
|
|
{
|
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_UVDPowerGating))
|
|
return smum_send_msg_to_smc(hwmgr->smumgr,
|
|
PPSMC_MSG_UVDPowerOFF);
|
|
return 0;
|
|
}
|
|
|
|
int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
|
|
{
|
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_UVDPowerGating)) {
|
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_UVDDynamicPowerGating)) {
|
|
return smum_send_msg_to_smc_with_parameter(
|
|
hwmgr->smumgr,
|
|
PPSMC_MSG_UVDPowerON, 1);
|
|
} else {
|
|
return smum_send_msg_to_smc_with_parameter(
|
|
hwmgr->smumgr,
|
|
PPSMC_MSG_UVDPowerON, 0);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
struct phm_uvd_clock_voltage_dependency_table *ptable =
|
|
hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
|
|
|
|
if (!bgate) {
|
|
/* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
|
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_StablePState)) {
|
|
cz_hwmgr->uvd_dpm.hard_min_clk =
|
|
ptable->entries[ptable->count - 1].vclk;
|
|
|
|
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_SetUvdHardMin,
|
|
cz_get_uvd_level(hwmgr,
|
|
cz_hwmgr->uvd_dpm.hard_min_clk,
|
|
PPSMC_MSG_SetUvdHardMin));
|
|
|
|
cz_enable_disable_uvd_dpm(hwmgr, true);
|
|
} else
|
|
cz_enable_disable_uvd_dpm(hwmgr, true);
|
|
} else
|
|
cz_enable_disable_uvd_dpm(hwmgr, false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
struct phm_vce_clock_voltage_dependency_table *ptable =
|
|
hwmgr->dyn_state.vce_clock_voltage_dependency_table;
|
|
|
|
/* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
|
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_StablePState)) {
|
|
cz_hwmgr->vce_dpm.hard_min_clk =
|
|
ptable->entries[ptable->count - 1].ecclk;
|
|
|
|
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_SetEclkHardMin,
|
|
cz_get_eclk_level(hwmgr,
|
|
cz_hwmgr->vce_dpm.hard_min_clk,
|
|
PPSMC_MSG_SetEclkHardMin));
|
|
} else {
|
|
/*EPR# 419220 -HW limitation to to */
|
|
cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
|
|
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_SetEclkHardMin,
|
|
cz_get_eclk_level(hwmgr,
|
|
cz_hwmgr->vce_dpm.hard_min_clk,
|
|
PPSMC_MSG_SetEclkHardMin));
|
|
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
|
|
{
|
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_VCEPowerGating))
|
|
return smum_send_msg_to_smc(hwmgr->smumgr,
|
|
PPSMC_MSG_VCEPowerOFF);
|
|
return 0;
|
|
}
|
|
|
|
int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
|
|
{
|
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_VCEPowerGating))
|
|
return smum_send_msg_to_smc(hwmgr->smumgr,
|
|
PPSMC_MSG_VCEPowerON);
|
|
return 0;
|
|
}
|
|
|
|
static int cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
|
|
return cz_hwmgr->sys_info.bootup_uma_clock;
|
|
}
|
|
|
|
static int cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
|
|
{
|
|
struct pp_power_state *ps;
|
|
struct cz_power_state *cz_ps;
|
|
|
|
if (hwmgr == NULL)
|
|
return -EINVAL;
|
|
|
|
ps = hwmgr->request_ps;
|
|
|
|
if (ps == NULL)
|
|
return -EINVAL;
|
|
|
|
cz_ps = cast_PhwCzPowerState(&ps->hardware);
|
|
|
|
if (low)
|
|
return cz_ps->levels[0].engineClock;
|
|
else
|
|
return cz_ps->levels[cz_ps->level-1].engineClock;
|
|
}
|
|
|
|
static int cz_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
|
|
struct pp_hw_power_state *hw_ps)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
|
|
|
|
cz_ps->level = 1;
|
|
cz_ps->nbps_flags = 0;
|
|
cz_ps->bapm_flags = 0;
|
|
cz_ps->levels[0] = cz_hwmgr->boot_power_level;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_dpm_get_pp_table_entry_callback(
|
|
struct pp_hwmgr *hwmgr,
|
|
struct pp_hw_power_state *hw_ps,
|
|
unsigned int index,
|
|
const void *clock_info)
|
|
{
|
|
struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
|
|
|
|
const ATOM_PPLIB_CZ_CLOCK_INFO *cz_clock_info = clock_info;
|
|
|
|
struct phm_clock_voltage_dependency_table *table =
|
|
hwmgr->dyn_state.vddc_dependency_on_sclk;
|
|
uint8_t clock_info_index = cz_clock_info->index;
|
|
|
|
if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
|
|
clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
|
|
|
|
cz_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
|
|
cz_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
|
|
|
|
cz_ps->level = index + 1;
|
|
|
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
|
|
cz_ps->levels[index].dsDividerIndex = 5;
|
|
cz_ps->levels[index].ssDividerIndex = 5;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
|
|
{
|
|
int result;
|
|
unsigned long ret = 0;
|
|
|
|
result = pp_tables_get_num_of_entries(hwmgr, &ret);
|
|
|
|
return result ? 0 : ret;
|
|
}
|
|
|
|
static int cz_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
|
|
unsigned long entry, struct pp_power_state *ps)
|
|
{
|
|
int result;
|
|
struct cz_power_state *cz_ps;
|
|
|
|
ps->hardware.magic = PhwCz_Magic;
|
|
|
|
cz_ps = cast_PhwCzPowerState(&(ps->hardware));
|
|
|
|
result = pp_tables_get_entry(hwmgr, entry, ps,
|
|
cz_dpm_get_pp_table_entry_callback);
|
|
|
|
cz_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
|
|
cz_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
|
|
|
|
return result;
|
|
}
|
|
|
|
int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
|
|
{
|
|
return sizeof(struct cz_power_state);
|
|
}
|
|
|
|
static void
|
|
cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
|
|
|
|
struct phm_clock_voltage_dependency_table *table =
|
|
hwmgr->dyn_state.vddc_dependency_on_sclk;
|
|
|
|
struct phm_vce_clock_voltage_dependency_table *vce_table =
|
|
hwmgr->dyn_state.vce_clock_voltage_dependency_table;
|
|
|
|
struct phm_uvd_clock_voltage_dependency_table *uvd_table =
|
|
hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
|
|
|
|
uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX),
|
|
TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
|
|
uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
|
|
TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
|
|
uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
|
|
TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
|
|
|
|
uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent;
|
|
uint16_t vddnb, vddgfx;
|
|
int result;
|
|
|
|
if (sclk_index >= NUM_SCLK_LEVELS) {
|
|
seq_printf(m, "\n invalid sclk dpm profile %d\n", sclk_index);
|
|
} else {
|
|
sclk = table->entries[sclk_index].clk;
|
|
seq_printf(m, "\n index: %u sclk: %u MHz\n", sclk_index, sclk/100);
|
|
}
|
|
|
|
tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
|
|
CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
|
|
vddnb = cz_convert_8Bit_index_to_voltage(hwmgr, tmp);
|
|
tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
|
|
CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
|
|
vddgfx = cz_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp);
|
|
seq_printf(m, "\n vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
|
|
|
|
seq_printf(m, "\n uvd %sabled\n", cz_hwmgr->uvd_power_gated ? "dis" : "en");
|
|
if (!cz_hwmgr->uvd_power_gated) {
|
|
if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
|
|
seq_printf(m, "\n invalid uvd dpm level %d\n", uvd_index);
|
|
} else {
|
|
vclk = uvd_table->entries[uvd_index].vclk;
|
|
dclk = uvd_table->entries[uvd_index].dclk;
|
|
seq_printf(m, "\n index: %u uvd vclk: %u MHz dclk: %u MHz\n", uvd_index, vclk/100, dclk/100);
|
|
}
|
|
}
|
|
|
|
seq_printf(m, "\n vce %sabled\n", cz_hwmgr->vce_power_gated ? "dis" : "en");
|
|
if (!cz_hwmgr->vce_power_gated) {
|
|
if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
|
|
seq_printf(m, "\n invalid vce dpm level %d\n", vce_index);
|
|
} else {
|
|
ecclk = vce_table->entries[vce_index].ecclk;
|
|
seq_printf(m, "\n index: %u vce ecclk: %u MHz\n", vce_index, ecclk/100);
|
|
}
|
|
}
|
|
|
|
result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity);
|
|
if (0 == result) {
|
|
activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
|
|
activity_percent = activity_percent > 100 ? 100 : activity_percent;
|
|
} else {
|
|
activity_percent = 50;
|
|
}
|
|
|
|
seq_printf(m, "\n [GPU load]: %u %%\n\n", activity_percent);
|
|
}
|
|
|
|
static void cz_hw_print_display_cfg(
|
|
const struct cc6_settings *cc6_settings)
|
|
{
|
|
PP_DBG_LOG("New Display Configuration:\n");
|
|
|
|
PP_DBG_LOG(" cpu_cc6_disable: %d\n",
|
|
cc6_settings->cpu_cc6_disable);
|
|
PP_DBG_LOG(" cpu_pstate_disable: %d\n",
|
|
cc6_settings->cpu_pstate_disable);
|
|
PP_DBG_LOG(" nb_pstate_switch_disable: %d\n",
|
|
cc6_settings->nb_pstate_switch_disable);
|
|
PP_DBG_LOG(" cpu_pstate_separation_time: %d\n\n",
|
|
cc6_settings->cpu_pstate_separation_time);
|
|
}
|
|
|
|
static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
|
|
{
|
|
struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
|
|
uint32_t data = 0;
|
|
|
|
if (hw_data->cc6_settings.cc6_setting_changed == true) {
|
|
|
|
hw_data->cc6_settings.cc6_setting_changed = false;
|
|
|
|
cz_hw_print_display_cfg(&hw_data->cc6_settings);
|
|
|
|
data |= (hw_data->cc6_settings.cpu_pstate_separation_time
|
|
& PWRMGT_SEPARATION_TIME_MASK)
|
|
<< PWRMGT_SEPARATION_TIME_SHIFT;
|
|
|
|
data|= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0)
|
|
<< PWRMGT_DISABLE_CPU_CSTATES_SHIFT;
|
|
|
|
data|= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0)
|
|
<< PWRMGT_DISABLE_CPU_PSTATES_SHIFT;
|
|
|
|
PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
|
|
data);
|
|
|
|
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
|
PPSMC_MSG_SetDisplaySizePowerParams,
|
|
data);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
|
|
bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
|
|
{
|
|
struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
|
|
|
|
if (separation_time !=
|
|
hw_data->cc6_settings.cpu_pstate_separation_time
|
|
|| cc6_disable !=
|
|
hw_data->cc6_settings.cpu_cc6_disable
|
|
|| pstate_disable !=
|
|
hw_data->cc6_settings.cpu_pstate_disable
|
|
|| pstate_switch_disable !=
|
|
hw_data->cc6_settings.nb_pstate_switch_disable) {
|
|
|
|
hw_data->cc6_settings.cc6_setting_changed = true;
|
|
|
|
hw_data->cc6_settings.cpu_pstate_separation_time =
|
|
separation_time;
|
|
hw_data->cc6_settings.cpu_cc6_disable =
|
|
cc6_disable;
|
|
hw_data->cc6_settings.cpu_pstate_disable =
|
|
pstate_disable;
|
|
hw_data->cc6_settings.nb_pstate_switch_disable =
|
|
pstate_switch_disable;
|
|
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
|
|
struct amd_pp_dal_clock_info*info)
|
|
{
|
|
uint32_t i;
|
|
const struct phm_clock_voltage_dependency_table * table =
|
|
hwmgr->dyn_state.vddc_dep_on_dal_pwrl;
|
|
const struct phm_clock_and_voltage_limits* limits =
|
|
&hwmgr->dyn_state.max_clock_voltage_on_ac;
|
|
|
|
info->engine_max_clock = limits->sclk;
|
|
info->memory_max_clock = limits->mclk;
|
|
|
|
for (i = table->count - 1; i > 0; i--) {
|
|
|
|
if (limits->vddc >= table->entries[i].v) {
|
|
info->level = table->entries[i].clk;
|
|
return 0;
|
|
}
|
|
}
|
|
return -EINVAL;
|
|
}
|
|
|
|
static const struct pp_hwmgr_func cz_hwmgr_funcs = {
|
|
.backend_init = cz_hwmgr_backend_init,
|
|
.backend_fini = cz_hwmgr_backend_fini,
|
|
.asic_setup = NULL,
|
|
.apply_state_adjust_rules = cz_apply_state_adjust_rules,
|
|
.force_dpm_level = cz_dpm_force_dpm_level,
|
|
.get_power_state_size = cz_get_power_state_size,
|
|
.powerdown_uvd = cz_dpm_powerdown_uvd,
|
|
.powergate_uvd = cz_dpm_powergate_uvd,
|
|
.powergate_vce = cz_dpm_powergate_vce,
|
|
.get_mclk = cz_dpm_get_mclk,
|
|
.get_sclk = cz_dpm_get_sclk,
|
|
.patch_boot_state = cz_dpm_patch_boot_state,
|
|
.get_pp_table_entry = cz_dpm_get_pp_table_entry,
|
|
.get_num_of_pp_table_entries = cz_dpm_get_num_of_pp_table_entries,
|
|
.print_current_perforce_level = cz_print_current_perforce_level,
|
|
.set_cpu_power_state = cz_set_cpu_power_state,
|
|
.store_cc6_data = cz_store_cc6_data,
|
|
.get_dal_power_level= cz_get_dal_power_level,
|
|
};
|
|
|
|
int cz_hwmgr_init(struct pp_hwmgr *hwmgr)
|
|
{
|
|
struct cz_hwmgr *cz_hwmgr;
|
|
int ret = 0;
|
|
|
|
cz_hwmgr = kzalloc(sizeof(struct cz_hwmgr), GFP_KERNEL);
|
|
if (cz_hwmgr == NULL)
|
|
return -ENOMEM;
|
|
|
|
hwmgr->backend = cz_hwmgr;
|
|
hwmgr->hwmgr_func = &cz_hwmgr_funcs;
|
|
hwmgr->pptable_func = &pptable_funcs;
|
|
return ret;
|
|
}
|