forked from Minki/linux
d2e1936884
When KVM panics, it hurridly restores the host context and parachutes
into the host's panic() code. This looks like it was copied from arm64,
the 32bit KVM panic code needs to restore the host's banked registers
too.
At some point panic() touches the physical timer/counter, this will
trap back to HYP. If we're lucky, we panic again.
Add a __timer_save_state() call to KVMs hyp_panic() path, this saves the
guest registers and disables the traps for the host.
Fixes: c36b6db5f3 ("ARM: KVM: Add panic handling code")
Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
250 lines
6.6 KiB
C
250 lines
6.6 KiB
C
/*
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* Copyright (C) 2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/jump_label.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_hyp.h>
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__asm__(".arch_extension virt");
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/*
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* Activate the traps, saving the host's fpexc register before
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* overwriting it. We'll restore it on VM exit.
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*/
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static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu, u32 *fpexc_host)
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{
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u32 val;
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/*
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* We are about to set HCPTR.TCP10/11 to trap all floating point
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* register accesses to HYP, however, the ARM ARM clearly states that
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* traps are only taken to HYP if the operation would not otherwise
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* trap to SVC. Therefore, always make sure that for 32-bit guests,
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* we set FPEXC.EN to prevent traps to SVC, when setting the TCP bits.
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*/
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val = read_sysreg(VFP_FPEXC);
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*fpexc_host = val;
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if (!(val & FPEXC_EN)) {
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write_sysreg(val | FPEXC_EN, VFP_FPEXC);
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isb();
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}
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write_sysreg(vcpu->arch.hcr | vcpu->arch.irq_lines, HCR);
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/* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */
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write_sysreg(HSTR_T(15), HSTR);
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write_sysreg(HCPTR_TTA | HCPTR_TCP(10) | HCPTR_TCP(11), HCPTR);
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val = read_sysreg(HDCR);
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write_sysreg(val | HDCR_TPM | HDCR_TPMCR, HDCR);
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}
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static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
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{
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u32 val;
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/*
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* If we pended a virtual abort, preserve it until it gets
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* cleared. See B1.9.9 (Virtual Abort exception) for details,
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* but the crucial bit is the zeroing of HCR.VA in the
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* pseudocode.
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*/
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if (vcpu->arch.hcr & HCR_VA)
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vcpu->arch.hcr = read_sysreg(HCR);
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write_sysreg(0, HCR);
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write_sysreg(0, HSTR);
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val = read_sysreg(HDCR);
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write_sysreg(val & ~(HDCR_TPM | HDCR_TPMCR), HDCR);
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write_sysreg(0, HCPTR);
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}
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static void __hyp_text __activate_vm(struct kvm_vcpu *vcpu)
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{
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struct kvm *kvm = kern_hyp_va(vcpu->kvm);
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write_sysreg(kvm->arch.vttbr, VTTBR);
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write_sysreg(vcpu->arch.midr, VPIDR);
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}
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static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu)
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{
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write_sysreg(0, VTTBR);
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write_sysreg(read_sysreg(MIDR), VPIDR);
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}
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static void __hyp_text __vgic_save_state(struct kvm_vcpu *vcpu)
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{
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if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
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__vgic_v3_save_state(vcpu);
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else
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__vgic_v2_save_state(vcpu);
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}
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static void __hyp_text __vgic_restore_state(struct kvm_vcpu *vcpu)
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{
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if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
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__vgic_v3_restore_state(vcpu);
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else
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__vgic_v2_restore_state(vcpu);
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}
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static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu)
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{
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u32 hsr = read_sysreg(HSR);
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u8 ec = hsr >> HSR_EC_SHIFT;
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u32 hpfar, far;
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vcpu->arch.fault.hsr = hsr;
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if (ec == HSR_EC_IABT)
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far = read_sysreg(HIFAR);
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else if (ec == HSR_EC_DABT)
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far = read_sysreg(HDFAR);
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else
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return true;
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/*
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* B3.13.5 Reporting exceptions taken to the Non-secure PL2 mode:
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*
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* Abort on the stage 2 translation for a memory access from a
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* Non-secure PL1 or PL0 mode:
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*
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* For any Access flag fault or Translation fault, and also for any
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* Permission fault on the stage 2 translation of a memory access
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* made as part of a translation table walk for a stage 1 translation,
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* the HPFAR holds the IPA that caused the fault. Otherwise, the HPFAR
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* is UNKNOWN.
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*/
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if (!(hsr & HSR_DABT_S1PTW) && (hsr & HSR_FSC_TYPE) == FSC_PERM) {
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u64 par, tmp;
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par = read_sysreg(PAR);
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write_sysreg(far, ATS1CPR);
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isb();
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tmp = read_sysreg(PAR);
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write_sysreg(par, PAR);
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if (unlikely(tmp & 1))
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return false; /* Translation failed, back to guest */
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hpfar = ((tmp >> 12) & ((1UL << 28) - 1)) << 4;
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} else {
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hpfar = read_sysreg(HPFAR);
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}
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vcpu->arch.fault.hxfar = far;
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vcpu->arch.fault.hpfar = hpfar;
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return true;
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}
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int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu)
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{
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struct kvm_cpu_context *host_ctxt;
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struct kvm_cpu_context *guest_ctxt;
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bool fp_enabled;
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u64 exit_code;
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u32 fpexc;
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vcpu = kern_hyp_va(vcpu);
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write_sysreg(vcpu, HTPIDR);
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host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
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guest_ctxt = &vcpu->arch.ctxt;
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__sysreg_save_state(host_ctxt);
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__banked_save_state(host_ctxt);
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__activate_traps(vcpu, &fpexc);
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__activate_vm(vcpu);
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__vgic_restore_state(vcpu);
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__timer_restore_state(vcpu);
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__sysreg_restore_state(guest_ctxt);
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__banked_restore_state(guest_ctxt);
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/* Jump in the fire! */
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again:
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exit_code = __guest_enter(vcpu, host_ctxt);
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/* And we're baaack! */
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if (exit_code == ARM_EXCEPTION_HVC && !__populate_fault_info(vcpu))
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goto again;
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fp_enabled = __vfp_enabled();
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__banked_save_state(guest_ctxt);
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__sysreg_save_state(guest_ctxt);
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__timer_save_state(vcpu);
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__vgic_save_state(vcpu);
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__deactivate_traps(vcpu);
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__deactivate_vm(vcpu);
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__banked_restore_state(host_ctxt);
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__sysreg_restore_state(host_ctxt);
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if (fp_enabled) {
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__vfp_save_state(&guest_ctxt->vfp);
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__vfp_restore_state(&host_ctxt->vfp);
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}
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write_sysreg(fpexc, VFP_FPEXC);
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return exit_code;
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}
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static const char * const __hyp_panic_string[] = {
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[ARM_EXCEPTION_RESET] = "\nHYP panic: RST PC:%08x CPSR:%08x",
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[ARM_EXCEPTION_UNDEFINED] = "\nHYP panic: UNDEF PC:%08x CPSR:%08x",
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[ARM_EXCEPTION_SOFTWARE] = "\nHYP panic: SVC PC:%08x CPSR:%08x",
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[ARM_EXCEPTION_PREF_ABORT] = "\nHYP panic: PABRT PC:%08x CPSR:%08x",
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[ARM_EXCEPTION_DATA_ABORT] = "\nHYP panic: DABRT PC:%08x ADDR:%08x",
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[ARM_EXCEPTION_IRQ] = "\nHYP panic: IRQ PC:%08x CPSR:%08x",
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[ARM_EXCEPTION_FIQ] = "\nHYP panic: FIQ PC:%08x CPSR:%08x",
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[ARM_EXCEPTION_HVC] = "\nHYP panic: HVC PC:%08x CPSR:%08x",
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};
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void __hyp_text __noreturn __hyp_panic(int cause)
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{
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u32 elr = read_special(ELR_hyp);
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u32 val;
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if (cause == ARM_EXCEPTION_DATA_ABORT)
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val = read_sysreg(HDFAR);
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else
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val = read_special(SPSR);
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if (read_sysreg(VTTBR)) {
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struct kvm_vcpu *vcpu;
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struct kvm_cpu_context *host_ctxt;
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vcpu = (struct kvm_vcpu *)read_sysreg(HTPIDR);
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host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
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__timer_save_state(vcpu);
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__deactivate_traps(vcpu);
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__deactivate_vm(vcpu);
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__banked_restore_state(host_ctxt);
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__sysreg_restore_state(host_ctxt);
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}
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/* Call panic for real */
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__hyp_do_panic(__hyp_panic_string[cause], elr, val);
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unreachable();
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}
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