forked from Minki/linux
c836e5cf0d
Intel Medfield may use common for Intel MID devices power sequence. Remove unneded custom power off stub. While here, remove function forward declaration. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/20170308112422.67533-1-andriy.shevchenko@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
71 lines
1.6 KiB
C
71 lines
1.6 KiB
C
/*
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* mfld.c: Intel Medfield platform setup code
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*
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* (C) Copyright 2013 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#include <linux/init.h>
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#include <asm/apic.h>
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#include <asm/intel-mid.h>
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#include <asm/intel_mid_vrtc.h>
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#include "intel_mid_weak_decls.h"
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static unsigned long __init mfld_calibrate_tsc(void)
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{
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unsigned long fast_calibrate;
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u32 lo, hi, ratio, fsb;
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rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
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pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi);
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ratio = (hi >> 8) & 0x1f;
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pr_debug("ratio is %d\n", ratio);
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if (!ratio) {
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pr_err("read a zero ratio, should be incorrect!\n");
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pr_err("force tsc ratio to 16 ...\n");
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ratio = 16;
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}
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rdmsr(MSR_FSB_FREQ, lo, hi);
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if ((lo & 0x7) == 0x7)
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fsb = FSB_FREQ_83SKU;
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else
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fsb = FSB_FREQ_100SKU;
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fast_calibrate = ratio * fsb;
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pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
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lapic_timer_frequency = fsb * 1000 / HZ;
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/*
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* TSC on Intel Atom SoCs is reliable and of known frequency.
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* See tsc_msr.c for details.
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*/
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setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
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setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
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return fast_calibrate;
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}
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static void __init penwell_arch_setup(void)
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{
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x86_platform.calibrate_tsc = mfld_calibrate_tsc;
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}
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static struct intel_mid_ops penwell_ops = {
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.arch_setup = penwell_arch_setup,
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};
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void *get_penwell_ops(void)
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{
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return &penwell_ops;
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}
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void *get_cloverview_ops(void)
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{
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return &penwell_ops;
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}
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