ab7c01fdc3
There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.
Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.
So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.
So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.
Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
493 lines
11 KiB
C
493 lines
11 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
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* Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
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* Copyright (C) 1999 Silicon Graphics, Inc.
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* Copyright (C) 2007 Maciej W. Rozycki
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*/
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#ifndef _ASM_STACKFRAME_H
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#define _ASM_STACKFRAME_H
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#include <linux/threads.h>
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/mipsregs.h>
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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/* Make the addition of cfi info a little easier. */
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.macro cfi_rel_offset reg offset=0 docfi=0
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.if \docfi
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.cfi_rel_offset \reg, \offset
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.endif
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.endm
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.macro cfi_st reg offset=0 docfi=0
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LONG_S \reg, \offset(sp)
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cfi_rel_offset \reg, \offset, \docfi
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.endm
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.macro cfi_restore reg offset=0 docfi=0
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.if \docfi
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.cfi_restore \reg
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.endif
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.endm
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.macro cfi_ld reg offset=0 docfi=0
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LONG_L \reg, \offset(sp)
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cfi_restore \reg \offset \docfi
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.endm
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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#define STATMASK 0x3f
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#else
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#define STATMASK 0x1f
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#endif
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.macro SAVE_AT docfi=0
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.set push
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.set noat
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cfi_st $1, PT_R1, \docfi
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.set pop
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.endm
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.macro SAVE_TEMP docfi=0
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#ifdef CONFIG_CPU_HAS_SMARTMIPS
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mflhxu v1
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LONG_S v1, PT_LO(sp)
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mflhxu v1
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LONG_S v1, PT_HI(sp)
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mflhxu v1
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LONG_S v1, PT_ACX(sp)
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#elif !defined(CONFIG_CPU_MIPSR6)
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mfhi v1
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#endif
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#ifdef CONFIG_32BIT
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cfi_st $8, PT_R8, \docfi
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cfi_st $9, PT_R9, \docfi
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#endif
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cfi_st $10, PT_R10, \docfi
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cfi_st $11, PT_R11, \docfi
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cfi_st $12, PT_R12, \docfi
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#if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
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LONG_S v1, PT_HI(sp)
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mflo v1
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#endif
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cfi_st $13, PT_R13, \docfi
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cfi_st $14, PT_R14, \docfi
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cfi_st $15, PT_R15, \docfi
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cfi_st $24, PT_R24, \docfi
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#if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
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LONG_S v1, PT_LO(sp)
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#endif
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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/*
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* The Octeon multiplier state is affected by general
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* multiply instructions. It must be saved before and
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* kernel code might corrupt it
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*/
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jal octeon_mult_save
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#endif
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.endm
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.macro SAVE_STATIC docfi=0
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cfi_st $16, PT_R16, \docfi
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cfi_st $17, PT_R17, \docfi
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cfi_st $18, PT_R18, \docfi
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cfi_st $19, PT_R19, \docfi
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cfi_st $20, PT_R20, \docfi
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cfi_st $21, PT_R21, \docfi
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cfi_st $22, PT_R22, \docfi
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cfi_st $23, PT_R23, \docfi
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cfi_st $30, PT_R30, \docfi
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.endm
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/*
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* get_saved_sp returns the SP for the current CPU by looking in the
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* kernelsp array for it. If tosp is set, it stores the current sp in
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* k0 and loads the new value in sp. If not, it clobbers k0 and
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* stores the new value in k1, leaving sp unaffected.
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*/
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#ifdef CONFIG_SMP
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/* SMP variation */
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.macro get_saved_sp docfi=0 tosp=0
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ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG
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#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
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lui k1, %hi(kernelsp)
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#else
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lui k1, %highest(kernelsp)
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daddiu k1, %higher(kernelsp)
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dsll k1, 16
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daddiu k1, %hi(kernelsp)
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dsll k1, 16
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#endif
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LONG_SRL k0, SMP_CPUID_PTRSHIFT
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LONG_ADDU k1, k0
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.if \tosp
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move k0, sp
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.if \docfi
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.cfi_register sp, k0
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.endif
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LONG_L sp, %lo(kernelsp)(k1)
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.else
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LONG_L k1, %lo(kernelsp)(k1)
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.endif
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.endm
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.macro set_saved_sp stackp temp temp2
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ASM_CPUID_MFC0 \temp, ASM_SMP_CPUID_REG
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LONG_SRL \temp, SMP_CPUID_PTRSHIFT
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LONG_S \stackp, kernelsp(\temp)
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.endm
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#else /* !CONFIG_SMP */
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/* Uniprocessor variation */
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.macro get_saved_sp docfi=0 tosp=0
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#ifdef CONFIG_CPU_JUMP_WORKAROUNDS
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/*
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* Clear BTB (branch target buffer), forbid RAS (return address
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* stack) to workaround the Out-of-order Issue in Loongson2F
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* via its diagnostic register.
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*/
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move k0, ra
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jal 1f
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nop
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1: jal 1f
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nop
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1: jal 1f
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nop
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1: jal 1f
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nop
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1: move ra, k0
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li k0, 3
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mtc0 k0, $22
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#endif /* CONFIG_CPU_JUMP_WORKAROUNDS */
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#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
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lui k1, %hi(kernelsp)
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#else
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lui k1, %highest(kernelsp)
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daddiu k1, %higher(kernelsp)
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dsll k1, k1, 16
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daddiu k1, %hi(kernelsp)
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dsll k1, k1, 16
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#endif
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.if \tosp
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move k0, sp
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.if \docfi
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.cfi_register sp, k0
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.endif
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LONG_L sp, %lo(kernelsp)(k1)
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.else
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LONG_L k1, %lo(kernelsp)(k1)
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.endif
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.endm
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.macro set_saved_sp stackp temp temp2
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LONG_S \stackp, kernelsp
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.endm
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#endif
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.macro SAVE_SOME docfi=0
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.set push
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.set noat
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.set reorder
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mfc0 k0, CP0_STATUS
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sll k0, 3 /* extract cu0 bit */
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.set noreorder
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bltz k0, 8f
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move k0, sp
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.if \docfi
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.cfi_register sp, k0
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.endif
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#ifdef CONFIG_EVA
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/*
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* Flush interAptiv's Return Prediction Stack (RPS) by writing
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* EntryHi. Toggling Config7.RPS is slower and less portable.
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*
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* The RPS isn't automatically flushed when exceptions are
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* taken, which can result in kernel mode speculative accesses
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* to user addresses if the RPS mispredicts. That's harmless
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* when user and kernel share the same address space, but with
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* EVA the same user segments may be unmapped to kernel mode,
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* even containing sensitive MMIO regions or invalid memory.
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*
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* This can happen when the kernel sets the return address to
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* ret_from_* and jr's to the exception handler, which looks
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* more like a tail call than a function call. If nested calls
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* don't evict the last user address in the RPS, it will
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* mispredict the return and fetch from a user controlled
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* address into the icache.
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*
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* More recent EVA-capable cores with MAAR to restrict
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* speculative accesses aren't affected.
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*/
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MFC0 k0, CP0_ENTRYHI
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MTC0 k0, CP0_ENTRYHI
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#endif
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.set reorder
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/* Called from user mode, new stack. */
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get_saved_sp docfi=\docfi tosp=1
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8:
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#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
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.set at=k1
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#endif
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PTR_SUBU sp, PT_SIZE
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#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
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.set noat
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#endif
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.if \docfi
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.cfi_def_cfa sp,0
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.endif
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cfi_st k0, PT_R29, \docfi
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cfi_rel_offset sp, PT_R29, \docfi
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cfi_st v1, PT_R3, \docfi
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/*
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* You might think that you don't need to save $0,
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* but the FPU emulator and gdb remote debug stub
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* need it to operate correctly
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*/
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LONG_S $0, PT_R0(sp)
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mfc0 v1, CP0_STATUS
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cfi_st v0, PT_R2, \docfi
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LONG_S v1, PT_STATUS(sp)
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cfi_st $4, PT_R4, \docfi
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mfc0 v1, CP0_CAUSE
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cfi_st $5, PT_R5, \docfi
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LONG_S v1, PT_CAUSE(sp)
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cfi_st $6, PT_R6, \docfi
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cfi_st ra, PT_R31, \docfi
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MFC0 ra, CP0_EPC
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cfi_st $7, PT_R7, \docfi
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#ifdef CONFIG_64BIT
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cfi_st $8, PT_R8, \docfi
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cfi_st $9, PT_R9, \docfi
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#endif
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LONG_S ra, PT_EPC(sp)
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.if \docfi
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.cfi_rel_offset ra, PT_EPC
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.endif
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cfi_st $25, PT_R25, \docfi
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cfi_st $28, PT_R28, \docfi
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/* Set thread_info if we're coming from user mode */
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mfc0 k0, CP0_STATUS
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sll k0, 3 /* extract cu0 bit */
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bltz k0, 9f
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ori $28, sp, _THREAD_MASK
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xori $28, _THREAD_MASK
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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.set mips64
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pref 0, 0($28) /* Prefetch the current pointer */
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#endif
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9:
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.set pop
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.endm
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.macro SAVE_ALL docfi=0
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SAVE_SOME \docfi
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SAVE_AT \docfi
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SAVE_TEMP \docfi
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SAVE_STATIC \docfi
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.endm
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.macro RESTORE_AT docfi=0
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.set push
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.set noat
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cfi_ld $1, PT_R1, \docfi
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.set pop
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.endm
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.macro RESTORE_TEMP docfi=0
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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/* Restore the Octeon multiplier state */
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jal octeon_mult_restore
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#endif
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#ifdef CONFIG_CPU_HAS_SMARTMIPS
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LONG_L $24, PT_ACX(sp)
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mtlhx $24
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LONG_L $24, PT_HI(sp)
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mtlhx $24
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LONG_L $24, PT_LO(sp)
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mtlhx $24
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#elif !defined(CONFIG_CPU_MIPSR6)
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LONG_L $24, PT_LO(sp)
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mtlo $24
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LONG_L $24, PT_HI(sp)
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mthi $24
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#endif
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#ifdef CONFIG_32BIT
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cfi_ld $8, PT_R8, \docfi
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cfi_ld $9, PT_R9, \docfi
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#endif
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cfi_ld $10, PT_R10, \docfi
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cfi_ld $11, PT_R11, \docfi
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cfi_ld $12, PT_R12, \docfi
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cfi_ld $13, PT_R13, \docfi
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cfi_ld $14, PT_R14, \docfi
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cfi_ld $15, PT_R15, \docfi
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cfi_ld $24, PT_R24, \docfi
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.endm
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.macro RESTORE_STATIC docfi=0
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cfi_ld $16, PT_R16, \docfi
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cfi_ld $17, PT_R17, \docfi
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cfi_ld $18, PT_R18, \docfi
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cfi_ld $19, PT_R19, \docfi
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cfi_ld $20, PT_R20, \docfi
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cfi_ld $21, PT_R21, \docfi
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cfi_ld $22, PT_R22, \docfi
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cfi_ld $23, PT_R23, \docfi
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cfi_ld $30, PT_R30, \docfi
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.endm
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.macro RESTORE_SP docfi=0
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cfi_ld sp, PT_R29, \docfi
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.endm
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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.macro RESTORE_SOME docfi=0
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.set push
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.set reorder
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.set noat
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mfc0 a0, CP0_STATUS
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li v1, ST0_CU1 | ST0_IM
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ori a0, STATMASK
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xori a0, STATMASK
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mtc0 a0, CP0_STATUS
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and a0, v1
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LONG_L v0, PT_STATUS(sp)
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nor v1, $0, v1
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and v0, v1
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or v0, a0
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mtc0 v0, CP0_STATUS
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cfi_ld $31, PT_R31, \docfi
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cfi_ld $28, PT_R28, \docfi
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cfi_ld $25, PT_R25, \docfi
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cfi_ld $7, PT_R7, \docfi
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cfi_ld $6, PT_R6, \docfi
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cfi_ld $5, PT_R5, \docfi
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cfi_ld $4, PT_R4, \docfi
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cfi_ld $3, PT_R3, \docfi
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cfi_ld $2, PT_R2, \docfi
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.set pop
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.endm
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.macro RESTORE_SP_AND_RET docfi=0
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.set push
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.set noreorder
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LONG_L k0, PT_EPC(sp)
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RESTORE_SP \docfi
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jr k0
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rfe
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.set pop
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.endm
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#else
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.macro RESTORE_SOME docfi=0
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.set push
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.set reorder
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.set noat
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mfc0 a0, CP0_STATUS
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ori a0, STATMASK
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xori a0, STATMASK
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mtc0 a0, CP0_STATUS
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li v1, ST0_CU1 | ST0_FR | ST0_IM
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and a0, v1
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LONG_L v0, PT_STATUS(sp)
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nor v1, $0, v1
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and v0, v1
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or v0, a0
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mtc0 v0, CP0_STATUS
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LONG_L v1, PT_EPC(sp)
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MTC0 v1, CP0_EPC
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cfi_ld $31, PT_R31, \docfi
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cfi_ld $28, PT_R28, \docfi
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cfi_ld $25, PT_R25, \docfi
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#ifdef CONFIG_64BIT
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cfi_ld $8, PT_R8, \docfi
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cfi_ld $9, PT_R9, \docfi
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#endif
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cfi_ld $7, PT_R7, \docfi
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cfi_ld $6, PT_R6, \docfi
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cfi_ld $5, PT_R5, \docfi
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cfi_ld $4, PT_R4, \docfi
|
|
cfi_ld $3, PT_R3, \docfi
|
|
cfi_ld $2, PT_R2, \docfi
|
|
.set pop
|
|
.endm
|
|
|
|
.macro RESTORE_SP_AND_RET docfi=0
|
|
RESTORE_SP \docfi
|
|
#if defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
|
|
eretnc
|
|
#else
|
|
.set push
|
|
.set arch=r4000
|
|
eret
|
|
.set pop
|
|
#endif
|
|
.endm
|
|
|
|
#endif
|
|
|
|
.macro RESTORE_ALL docfi=0
|
|
RESTORE_TEMP \docfi
|
|
RESTORE_STATIC \docfi
|
|
RESTORE_AT \docfi
|
|
RESTORE_SOME \docfi
|
|
RESTORE_SP \docfi
|
|
.endm
|
|
|
|
/*
|
|
* Move to kernel mode and disable interrupts.
|
|
* Set cp0 enable bit as sign that we're running on the kernel stack
|
|
*/
|
|
.macro CLI
|
|
mfc0 t0, CP0_STATUS
|
|
li t1, ST0_CU0 | STATMASK
|
|
or t0, t1
|
|
xori t0, STATMASK
|
|
mtc0 t0, CP0_STATUS
|
|
irq_disable_hazard
|
|
.endm
|
|
|
|
/*
|
|
* Move to kernel mode and enable interrupts.
|
|
* Set cp0 enable bit as sign that we're running on the kernel stack
|
|
*/
|
|
.macro STI
|
|
mfc0 t0, CP0_STATUS
|
|
li t1, ST0_CU0 | STATMASK
|
|
or t0, t1
|
|
xori t0, STATMASK & ~1
|
|
mtc0 t0, CP0_STATUS
|
|
irq_enable_hazard
|
|
.endm
|
|
|
|
/*
|
|
* Just move to kernel mode and leave interrupts as they are. Note
|
|
* for the R3000 this means copying the previous enable from IEp.
|
|
* Set cp0 enable bit as sign that we're running on the kernel stack
|
|
*/
|
|
.macro KMODE
|
|
mfc0 t0, CP0_STATUS
|
|
li t1, ST0_CU0 | (STATMASK & ~1)
|
|
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
|
|
andi t2, t0, ST0_IEP
|
|
srl t2, 2
|
|
or t0, t2
|
|
#endif
|
|
or t0, t1
|
|
xori t0, STATMASK & ~1
|
|
mtc0 t0, CP0_STATUS
|
|
irq_disable_hazard
|
|
.endm
|
|
|
|
#endif /* _ASM_STACKFRAME_H */
|