Wayne Lin d1fa156809 drm/amd/display: Support vertical interrupt 0 for all dcn ASIC ... [Why] When CONFIG_DRM_AMD_SECURE_DISPLAY is enabled, it will try to register vertical interrupt 0 for specific task. Currently, only dcn10 have defined relevant info for vertical interrupt 0. If we enable CONFIG_DRM_AMD_SECURE_DISPLAY for other dcn ASIC, will get DC_IRQ_SOURCE_INVALID while calling dc_interrupt_to_irq_source() and cause pointer errors. [How] Add support of vertical interrupt 0 for all dcn ASIC. v2: squash in build fix (Alex) Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-03-23 23:36:31 -04:00
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acp	drm: amd/acp: fix broken menu structure	2020-03-13 11:52:35 -04:00
amdgpu	drm/amdgpu/display: re-enable freesync video patches	2021-03-23 23:36:10 -04:00
amdkfd	drm/amdkfd: fix build error with AMD_IOMMU_V2=m	2021-03-23 23:28:11 -04:00
display	drm/amd/display: Support vertical interrupt 0 for all dcn ASIC	2021-03-23 23:36:31 -04:00
include	drm/amd/pm: add a new sysfs entry for default power limit	2021-03-23 23:30:55 -04:00
pm	drm/amd/pm: correct the gpu metrics version	2021-03-23 23:36:20 -04:00