acddfc2c26
Add MT8183 clock support, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
57 lines
1.5 KiB
C
57 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2018 MediaTek Inc.
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// Author: Weiyi Lu <weiyi.lu@mediatek.com>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt8183-clk.h>
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static const struct mtk_gate_regs ipu_core0_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_IPU_CORE0(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &ipu_core0_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr)
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static const struct mtk_gate ipu_core0_clks[] = {
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GATE_IPU_CORE0(CLK_IPU_CORE0_JTAG, "ipu_core0_jtag", "dsp_sel", 0),
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GATE_IPU_CORE0(CLK_IPU_CORE0_AXI, "ipu_core0_axi", "dsp_sel", 1),
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GATE_IPU_CORE0(CLK_IPU_CORE0_IPU, "ipu_core0_ipu", "dsp_sel", 2),
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};
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static int clk_mt8183_ipu_core0_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_IPU_CORE0_NR_CLK);
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mtk_clk_register_gates(node, ipu_core0_clks, ARRAY_SIZE(ipu_core0_clks),
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clk_data);
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return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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static const struct of_device_id of_match_clk_mt8183_ipu_core0[] = {
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{ .compatible = "mediatek,mt8183-ipu_core0", },
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{}
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};
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static struct platform_driver clk_mt8183_ipu_core0_drv = {
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.probe = clk_mt8183_ipu_core0_probe,
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.driver = {
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.name = "clk-mt8183-ipu_core0",
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.of_match_table = of_match_clk_mt8183_ipu_core0,
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},
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};
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builtin_platform_driver(clk_mt8183_ipu_core0_drv);
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