forked from Minki/linux
d0f5de6677
This patch adds missing divider/gate clocks of CMU_PERIC domain which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use external input clock which has 'ioclk_*' prefix. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> [ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on] Signed-off-by: Inha Song <ideal.song@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
259 lines
7.2 KiB
C
259 lines
7.2 KiB
C
/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* Author: Chanwoo Choi <cw00.choi@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H
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#define _DT_BINDINGS_CLOCK_EXYNOS5433_H
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/* CMU_TOP */
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#define CLK_FOUT_ISP_PLL 1
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#define CLK_FOUT_AUD_PLL 2
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#define CLK_MOUT_AUD_PLL 10
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#define CLK_MOUT_ISP_PLL 11
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#define CLK_MOUT_AUD_PLL_USER_T 12
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#define CLK_MOUT_MPHY_PLL_USER 13
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#define CLK_MOUT_MFC_PLL_USER 14
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#define CLK_MOUT_BUS_PLL_USER 15
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#define CLK_MOUT_ACLK_HEVC_400 16
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#define CLK_MOUT_ACLK_CAM1_333 17
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#define CLK_MOUT_ACLK_CAM1_552_B 18
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#define CLK_MOUT_ACLK_CAM1_552_A 19
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#define CLK_MOUT_ACLK_ISP_DIS_400 20
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#define CLK_MOUT_ACLK_ISP_400 21
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#define CLK_MOUT_ACLK_BUS0_400 22
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#define CLK_MOUT_ACLK_MSCL_400_B 23
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#define CLK_MOUT_ACLK_MSCL_400_A 24
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#define CLK_MOUT_ACLK_GSCL_333 25
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#define CLK_MOUT_ACLK_G2D_400_B 26
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#define CLK_MOUT_ACLK_G2D_400_A 27
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#define CLK_MOUT_SCLK_JPEG_C 28
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#define CLK_MOUT_SCLK_JPEG_B 29
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#define CLK_MOUT_SCLK_JPEG_A 30
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#define CLK_MOUT_SCLK_MMC2_B 31
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#define CLK_MOUT_SCLK_MMC2_A 32
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#define CLK_MOUT_SCLK_MMC1_B 33
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#define CLK_MOUT_SCLK_MMC1_A 34
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#define CLK_MOUT_SCLK_MMC0_D 35
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#define CLK_MOUT_SCLK_MMC0_C 36
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#define CLK_MOUT_SCLK_MMC0_B 37
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#define CLK_MOUT_SCLK_MMC0_A 38
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#define CLK_MOUT_SCLK_SPI4 39
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#define CLK_MOUT_SCLK_SPI3 40
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#define CLK_MOUT_SCLK_UART2 41
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#define CLK_MOUT_SCLK_UART1 42
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#define CLK_MOUT_SCLK_UART0 43
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#define CLK_MOUT_SCLK_SPI2 44
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#define CLK_MOUT_SCLK_SPI1 45
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#define CLK_MOUT_SCLK_SPI0 46
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#define CLK_MOUT_ACLK_MFC_400_C 47
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#define CLK_MOUT_ACLK_MFC_400_B 48
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#define CLK_MOUT_ACLK_MFC_400_A 49
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#define CLK_MOUT_SCLK_ISP_SENSOR2 50
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#define CLK_MOUT_SCLK_ISP_SENSOR1 51
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#define CLK_MOUT_SCLK_ISP_SENSOR0 52
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#define CLK_MOUT_SCLK_ISP_UART 53
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#define CLK_MOUT_SCLK_ISP_SPI1 54
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#define CLK_MOUT_SCLK_ISP_SPI0 55
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#define CLK_MOUT_SCLK_PCIE_100 56
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#define CLK_MOUT_SCLK_UFSUNIPRO 57
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#define CLK_MOUT_SCLK_USBHOST30 58
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#define CLK_MOUT_SCLK_USBDRD30 59
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#define CLK_MOUT_SCLK_SLIMBUS 60
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#define CLK_MOUT_SCLK_SPDIF 61
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#define CLK_MOUT_SCLK_AUDIO1 62
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#define CLK_MOUT_SCLK_AUDIO0 63
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#define CLK_DIV_ACLK_FSYS_200 100
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#define CLK_DIV_ACLK_IMEM_SSSX_266 101
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#define CLK_DIV_ACLK_IMEM_200 102
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#define CLK_DIV_ACLK_IMEM_266 103
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#define CLK_DIV_ACLK_PERIC_66_B 104
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#define CLK_DIV_ACLK_PERIC_66_A 105
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#define CLK_DIV_ACLK_PERIS_66_B 106
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#define CLK_DIV_ACLK_PERIS_66_A 107
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#define CLK_DIV_SCLK_MMC1_B 108
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#define CLK_DIV_SCLK_MMC1_A 109
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#define CLK_DIV_SCLK_MMC0_B 110
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#define CLK_DIV_SCLK_MMC0_A 111
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#define CLK_DIV_SCLK_MMC2_B 112
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#define CLK_DIV_SCLK_MMC2_A 113
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#define CLK_DIV_SCLK_SPI1_B 114
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#define CLK_DIV_SCLK_SPI1_A 115
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#define CLK_DIV_SCLK_SPI0_B 116
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#define CLK_DIV_SCLK_SPI0_A 117
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#define CLK_DIV_SCLK_SPI2_B 118
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#define CLK_DIV_SCLK_SPI2_A 119
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#define CLK_DIV_SCLK_UART2 120
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#define CLK_DIV_SCLK_UART1 121
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#define CLK_DIV_SCLK_UART0 122
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#define CLK_DIV_SCLK_SPI4_B 123
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#define CLK_DIV_SCLK_SPI4_A 124
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#define CLK_DIV_SCLK_SPI3_B 125
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#define CLK_DIV_SCLK_SPI3_A 126
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#define CLK_DIV_SCLK_I2S1 127
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#define CLK_DIV_SCLK_PCM1 128
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#define CLK_DIV_SCLK_AUDIO1 129
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#define CLK_DIV_SCLK_AUDIO0 130
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#define CLK_ACLK_PERIC_66 200
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#define CLK_ACLK_PERIS_66 201
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#define CLK_ACLK_FSYS_200 202
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#define CLK_SCLK_MMC2_FSYS 203
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#define CLK_SCLK_MMC1_FSYS 204
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#define CLK_SCLK_MMC0_FSYS 205
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#define CLK_SCLK_SPI4_PERIC 206
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#define CLK_SCLK_SPI3_PERIC 207
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#define CLK_SCLK_UART2_PERIC 208
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#define CLK_SCLK_UART1_PERIC 209
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#define CLK_SCLK_UART0_PERIC 210
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#define CLK_SCLK_SPI2_PERIC 211
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#define CLK_SCLK_SPI1_PERIC 212
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#define CLK_SCLK_SPI0_PERIC 213
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#define CLK_SCLK_SPDIF_PERIC 214
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#define CLK_SCLK_I2S1_PERIC 215
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#define CLK_SCLK_PCM1_PERIC 216
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#define CLK_SCLK_SLIMBUS 217
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#define CLK_SCLK_AUDIO1 218
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#define CLK_SCLK_AUDIO0 219
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#define TOP_NR_CLK 220
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/* CMU_CPIF */
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#define CLK_FOUT_MPHY_PLL 1
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#define CLK_MOUT_MPHY_PLL 2
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#define CLK_DIV_SCLK_MPHY 10
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#define CLK_SCLK_MPHY_PLL 11
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#define CLK_SCLK_UFS_MPHY 11
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#define CPIF_NR_CLK 12
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/* CMU_MIF */
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#define CLK_FOUT_MEM0_PLL 1
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#define CLK_FOUT_MEM1_PLL 2
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#define CLK_FOUT_BUS_PLL 3
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#define CLK_FOUT_MFC_PLL 4
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#define MIF_NR_CLK 5
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/* CMU_PERIC */
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#define CLK_PCLK_SPI2 1
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#define CLK_PCLK_SPI1 2
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#define CLK_PCLK_SPI0 3
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#define CLK_PCLK_UART2 4
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#define CLK_PCLK_UART1 5
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#define CLK_PCLK_UART0 6
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#define CLK_PCLK_HSI2C3 7
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#define CLK_PCLK_HSI2C2 8
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#define CLK_PCLK_HSI2C1 9
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#define CLK_PCLK_HSI2C0 10
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#define CLK_PCLK_I2C7 11
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#define CLK_PCLK_I2C6 12
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#define CLK_PCLK_I2C5 13
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#define CLK_PCLK_I2C4 14
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#define CLK_PCLK_I2C3 15
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#define CLK_PCLK_I2C2 16
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#define CLK_PCLK_I2C1 17
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#define CLK_PCLK_I2C0 18
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#define CLK_PCLK_SPI4 19
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#define CLK_PCLK_SPI3 20
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#define CLK_PCLK_HSI2C11 21
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#define CLK_PCLK_HSI2C10 22
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#define CLK_PCLK_HSI2C9 23
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#define CLK_PCLK_HSI2C8 24
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#define CLK_PCLK_HSI2C7 25
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#define CLK_PCLK_HSI2C6 26
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#define CLK_PCLK_HSI2C5 27
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#define CLK_PCLK_HSI2C4 28
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#define CLK_SCLK_SPI4 29
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#define CLK_SCLK_SPI3 30
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#define CLK_SCLK_SPI2 31
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#define CLK_SCLK_SPI1 32
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#define CLK_SCLK_SPI0 33
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#define CLK_SCLK_UART2 34
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#define CLK_SCLK_UART1 35
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#define CLK_SCLK_UART0 36
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#define CLK_ACLK_AHB2APB_PERIC2P 37
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#define CLK_ACLK_AHB2APB_PERIC1P 38
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#define CLK_ACLK_AHB2APB_PERIC0P 39
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#define CLK_ACLK_PERICNP_66 40
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#define CLK_PCLK_SCI 41
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#define CLK_PCLK_GPIO_FINGER 42
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#define CLK_PCLK_GPIO_ESE 43
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#define CLK_PCLK_PWM 44
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#define CLK_PCLK_SPDIF 45
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#define CLK_PCLK_PCM1 46
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#define CLK_PCLK_I2S1 47
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#define CLK_PCLK_ADCIF 48
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#define CLK_PCLK_GPIO_TOUCH 49
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#define CLK_PCLK_GPIO_NFC 50
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#define CLK_PCLK_GPIO_PERIC 51
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#define CLK_PCLK_PMU_PERIC 52
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#define CLK_PCLK_SYSREG_PERIC 53
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#define CLK_SCLK_IOCLK_SPI4 54
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#define CLK_SCLK_IOCLK_SPI3 55
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#define CLK_SCLK_SCI 56
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#define CLK_SCLK_SC_IN 57
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#define CLK_SCLK_PWM 58
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#define CLK_SCLK_IOCLK_SPI2 59
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#define CLK_SCLK_IOCLK_SPI1 60
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#define CLK_SCLK_IOCLK_SPI0 61
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#define CLK_SCLK_IOCLK_I2S1_BCLK 62
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#define CLK_SCLK_SPDIF 63
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#define CLK_SCLK_PCM1 64
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#define CLK_SCLK_I2S1 65
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#define CLK_DIV_SCLK_SCI 70
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#define CLK_DIV_SCLK_SC_IN 71
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#define PERIC_NR_CLK 72
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/* CMU_PERIS */
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#define CLK_PCLK_HPM_APBIF 1
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#define CLK_PCLK_TMU1_APBIF 2
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#define CLK_PCLK_TMU0_APBIF 3
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#define CLK_PCLK_PMU_PERIS 4
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#define CLK_PCLK_SYSREG_PERIS 5
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#define CLK_PCLK_CMU_TOP_APBIF 6
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#define CLK_PCLK_WDT_APOLLO 7
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#define CLK_PCLK_WDT_ATLAS 8
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#define CLK_PCLK_MCT 9
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#define CLK_PCLK_HDMI_CEC 10
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#define PERIS_NR_CLK 11
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/* CMU_FSYS */
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#define CLK_MOUT_ACLK_FSYS_200_USER 1
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#define CLK_MOUT_SCLK_MMC2_USER 2
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#define CLK_MOUT_SCLK_MMC1_USER 3
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#define CLK_MOUT_SCLK_MMC0_USER 4
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#define CLK_ACLK_PCIE 50
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#define CLK_ACLK_PDMA1 51
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#define CLK_ACLK_TSI 52
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#define CLK_ACLK_MMC2 53
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#define CLK_ACLK_MMC1 54
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#define CLK_ACLK_MMC0 55
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#define CLK_ACLK_UFS 56
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#define CLK_ACLK_USBHOST20 57
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#define CLK_ACLK_USBHOST30 58
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#define CLK_ACLK_USBDRD30 59
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#define CLK_ACLK_PDMA0 60
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#define CLK_SCLK_MMC2 61
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#define CLK_SCLK_MMC1 62
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#define CLK_SCLK_MMC0 63
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#define CLK_PDMA1 64
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#define CLK_PDMA0 65
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#define FSYS_NR_CLK 66
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
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