forked from Minki/linux
f5eda47f45
This patch distributes the Local Oscillator calibration bursts over time, so that calibration only happens when it's actually needed. Currently we periodically perform a recalibration of the whole table. The table is huge and this takes lots of time. Additionally only small bits of the table are actually needed at a given time. So instead of maintaining a huge table with all possible calibration values, we create dynamic calibration settings that a) We only calibrate when they are actually needed. b) Are cached for some time until they expire. So a recalibration might happen if we need a calibration setting that's not cached, or if the active calibration setting expires. Currently the expire timeout is set to 30 seconds. We may raise that in future. This patch reduces overall memory consumption by nuking the huge static calibration tables. This patch has been tested on several 4306, 4311 and 4318 flavours. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
341 lines
14 KiB
C
341 lines
14 KiB
C
#ifndef B43_PHY_H_
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#define B43_PHY_H_
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#include <linux/types.h>
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struct b43_wldev;
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struct b43_phy;
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/*** PHY Registers ***/
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/* Routing */
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#define B43_PHYROUTE 0x0C00 /* PHY register routing bits mask */
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#define B43_PHYROUTE_BASE 0x0000 /* Base registers */
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#define B43_PHYROUTE_OFDM_GPHY 0x0400 /* OFDM register routing for G-PHYs */
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#define B43_PHYROUTE_EXT_GPHY 0x0800 /* Extended G-PHY registers */
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#define B43_PHYROUTE_N_BMODE 0x0C00 /* N-PHY BMODE registers */
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/* CCK (B-PHY) registers. */
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#define B43_PHY_CCK(reg) ((reg) | B43_PHYROUTE_BASE)
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/* N-PHY registers. */
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#define B43_PHY_N(reg) ((reg) | B43_PHYROUTE_BASE)
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/* N-PHY BMODE registers. */
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#define B43_PHY_N_BMODE(reg) ((reg) | B43_PHYROUTE_N_BMODE)
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/* OFDM (A-PHY) registers. */
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#define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY)
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/* Extended G-PHY registers. */
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#define B43_PHY_EXTG(reg) ((reg) | B43_PHYROUTE_EXT_GPHY)
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/* OFDM (A) PHY Registers */
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#define B43_PHY_VERSION_OFDM B43_PHY_OFDM(0x00) /* Versioning register for A-PHY */
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#define B43_PHY_BBANDCFG B43_PHY_OFDM(0x01) /* Baseband config */
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#define B43_PHY_BBANDCFG_RXANT 0x180 /* RX Antenna selection */
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#define B43_PHY_BBANDCFG_RXANT_SHIFT 7
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#define B43_PHY_PWRDOWN B43_PHY_OFDM(0x03) /* Powerdown */
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#define B43_PHY_CRSTHRES1_R1 B43_PHY_OFDM(0x06) /* CRS Threshold 1 (phy.rev 1 only) */
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#define B43_PHY_LNAHPFCTL B43_PHY_OFDM(0x1C) /* LNA/HPF control */
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#define B43_PHY_LPFGAINCTL B43_PHY_OFDM(0x20) /* LPF Gain control */
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#define B43_PHY_ADIVRELATED B43_PHY_OFDM(0x27) /* FIXME rename */
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#define B43_PHY_CRS0 B43_PHY_OFDM(0x29)
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#define B43_PHY_CRS0_EN 0x4000
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#define B43_PHY_PEAK_COUNT B43_PHY_OFDM(0x30)
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#define B43_PHY_ANTDWELL B43_PHY_OFDM(0x2B) /* Antenna dwell */
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#define B43_PHY_ANTDWELL_AUTODIV1 0x0100 /* Automatic RX diversity start antenna */
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#define B43_PHY_ENCORE B43_PHY_OFDM(0x49) /* "Encore" (RangeMax / BroadRange) */
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#define B43_PHY_ENCORE_EN 0x0200 /* Encore enable */
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#define B43_PHY_LMS B43_PHY_OFDM(0x55)
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#define B43_PHY_OFDM61 B43_PHY_OFDM(0x61) /* FIXME rename */
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#define B43_PHY_OFDM61_10 0x0010 /* FIXME rename */
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#define B43_PHY_IQBAL B43_PHY_OFDM(0x69) /* I/Q balance */
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#define B43_PHY_BBTXDC_BIAS B43_PHY_OFDM(0x6B) /* Baseband TX DC bias */
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#define B43_PHY_OTABLECTL B43_PHY_OFDM(0x72) /* OFDM table control (see below) */
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#define B43_PHY_OTABLEOFF 0x03FF /* OFDM table offset (see below) */
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#define B43_PHY_OTABLENR 0xFC00 /* OFDM table number (see below) */
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#define B43_PHY_OTABLENR_SHIFT 10
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#define B43_PHY_OTABLEI B43_PHY_OFDM(0x73) /* OFDM table data I */
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#define B43_PHY_OTABLEQ B43_PHY_OFDM(0x74) /* OFDM table data Q */
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#define B43_PHY_HPWR_TSSICTL B43_PHY_OFDM(0x78) /* Hardware power TSSI control */
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#define B43_PHY_ADCCTL B43_PHY_OFDM(0x7A) /* ADC control */
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#define B43_PHY_IDLE_TSSI B43_PHY_OFDM(0x7B)
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#define B43_PHY_A_TEMP_SENSE B43_PHY_OFDM(0x7C) /* A PHY temperature sense */
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#define B43_PHY_NRSSITHRES B43_PHY_OFDM(0x8A) /* NRSSI threshold */
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#define B43_PHY_ANTWRSETT B43_PHY_OFDM(0x8C) /* Antenna WR settle */
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#define B43_PHY_ANTWRSETT_ARXDIV 0x2000 /* Automatic RX diversity enabled */
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#define B43_PHY_CLIPPWRDOWNT B43_PHY_OFDM(0x93) /* Clip powerdown threshold */
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#define B43_PHY_OFDM9B B43_PHY_OFDM(0x9B) /* FIXME rename */
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#define B43_PHY_N1P1GAIN B43_PHY_OFDM(0xA0)
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#define B43_PHY_P1P2GAIN B43_PHY_OFDM(0xA1)
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#define B43_PHY_N1N2GAIN B43_PHY_OFDM(0xA2)
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#define B43_PHY_CLIPTHRES B43_PHY_OFDM(0xA3)
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#define B43_PHY_CLIPN1P2THRES B43_PHY_OFDM(0xA4)
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#define B43_PHY_CCKSHIFTBITS_WA B43_PHY_OFDM(0xA5) /* CCK shiftbits workaround, FIXME rename */
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#define B43_PHY_CCKSHIFTBITS B43_PHY_OFDM(0xA7) /* FIXME rename */
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#define B43_PHY_DIVSRCHIDX B43_PHY_OFDM(0xA8) /* Divider search gain/index */
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#define B43_PHY_CLIPP2THRES B43_PHY_OFDM(0xA9)
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#define B43_PHY_CLIPP3THRES B43_PHY_OFDM(0xAA)
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#define B43_PHY_DIVP1P2GAIN B43_PHY_OFDM(0xAB)
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#define B43_PHY_DIVSRCHGAINBACK B43_PHY_OFDM(0xAD) /* Divider search gain back */
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#define B43_PHY_DIVSRCHGAINCHNG B43_PHY_OFDM(0xAE) /* Divider search gain change */
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#define B43_PHY_CRSTHRES1 B43_PHY_OFDM(0xC0) /* CRS Threshold 1 (phy.rev >= 2 only) */
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#define B43_PHY_CRSTHRES2 B43_PHY_OFDM(0xC1) /* CRS Threshold 2 (phy.rev >= 2 only) */
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#define B43_PHY_TSSIP_LTBASE B43_PHY_OFDM(0x380) /* TSSI power lookup table base */
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#define B43_PHY_DC_LTBASE B43_PHY_OFDM(0x3A0) /* DC lookup table base */
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#define B43_PHY_GAIN_LTBASE B43_PHY_OFDM(0x3C0) /* Gain lookup table base */
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/* CCK (B) PHY Registers */
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#define B43_PHY_VERSION_CCK B43_PHY_CCK(0x00) /* Versioning register for B-PHY */
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#define B43_PHY_CCKBBANDCFG B43_PHY_CCK(0x01) /* Contains antenna 0/1 control bit */
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#define B43_PHY_PGACTL B43_PHY_CCK(0x15) /* PGA control */
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#define B43_PHY_PGACTL_LPF 0x1000 /* Low pass filter (?) */
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#define B43_PHY_PGACTL_LOWBANDW 0x0040 /* Low bandwidth flag */
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#define B43_PHY_PGACTL_UNKNOWN 0xEFA0
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#define B43_PHY_FBCTL1 B43_PHY_CCK(0x18) /* Frequency bandwidth control 1 */
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#define B43_PHY_ITSSI B43_PHY_CCK(0x29) /* Idle TSSI */
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#define B43_PHY_LO_LEAKAGE B43_PHY_CCK(0x2D) /* Measured LO leakage */
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#define B43_PHY_ENERGY B43_PHY_CCK(0x33) /* Energy */
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#define B43_PHY_SYNCCTL B43_PHY_CCK(0x35)
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#define B43_PHY_FBCTL2 B43_PHY_CCK(0x38) /* Frequency bandwidth control 2 */
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#define B43_PHY_DACCTL B43_PHY_CCK(0x60) /* DAC control */
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#define B43_PHY_RCCALOVER B43_PHY_CCK(0x78) /* RC calibration override */
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/* Extended G-PHY Registers */
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#define B43_PHY_CLASSCTL B43_PHY_EXTG(0x02) /* Classify control */
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#define B43_PHY_GTABCTL B43_PHY_EXTG(0x03) /* G-PHY table control (see below) */
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#define B43_PHY_GTABOFF 0x03FF /* G-PHY table offset (see below) */
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#define B43_PHY_GTABNR 0xFC00 /* G-PHY table number (see below) */
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#define B43_PHY_GTABNR_SHIFT 10
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#define B43_PHY_GTABDATA B43_PHY_EXTG(0x04) /* G-PHY table data */
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#define B43_PHY_LO_MASK B43_PHY_EXTG(0x0F) /* Local Oscillator control mask */
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#define B43_PHY_LO_CTL B43_PHY_EXTG(0x10) /* Local Oscillator control */
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#define B43_PHY_RFOVER B43_PHY_EXTG(0x11) /* RF override */
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#define B43_PHY_RFOVERVAL B43_PHY_EXTG(0x12) /* RF override value */
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#define B43_PHY_RFOVERVAL_EXTLNA 0x8000
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#define B43_PHY_RFOVERVAL_LNA 0x7000
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#define B43_PHY_RFOVERVAL_LNA_SHIFT 12
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#define B43_PHY_RFOVERVAL_PGA 0x0F00
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#define B43_PHY_RFOVERVAL_PGA_SHIFT 8
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#define B43_PHY_RFOVERVAL_UNK 0x0010 /* Unknown, always set. */
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#define B43_PHY_RFOVERVAL_TRSWRX 0x00E0
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#define B43_PHY_RFOVERVAL_BW 0x0003 /* Bandwidth flags */
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#define B43_PHY_RFOVERVAL_BW_LPF 0x0001 /* Low Pass Filter */
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#define B43_PHY_RFOVERVAL_BW_LBW 0x0002 /* Low Bandwidth (when set), high when unset */
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#define B43_PHY_ANALOGOVER B43_PHY_EXTG(0x14) /* Analog override */
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#define B43_PHY_ANALOGOVERVAL B43_PHY_EXTG(0x15) /* Analog override value */
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/*** OFDM table numbers ***/
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#define B43_OFDMTAB(number, offset) (((number) << B43_PHY_OTABLENR_SHIFT) | (offset))
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#define B43_OFDMTAB_AGC1 B43_OFDMTAB(0x00, 0)
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#define B43_OFDMTAB_GAIN0 B43_OFDMTAB(0x00, 0)
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#define B43_OFDMTAB_GAINX B43_OFDMTAB(0x01, 0) //TODO rename
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#define B43_OFDMTAB_GAIN1 B43_OFDMTAB(0x01, 4)
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#define B43_OFDMTAB_AGC3 B43_OFDMTAB(0x02, 0)
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#define B43_OFDMTAB_GAIN2 B43_OFDMTAB(0x02, 3)
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#define B43_OFDMTAB_LNAHPFGAIN1 B43_OFDMTAB(0x03, 0)
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#define B43_OFDMTAB_WRSSI B43_OFDMTAB(0x04, 0)
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#define B43_OFDMTAB_LNAHPFGAIN2 B43_OFDMTAB(0x04, 0)
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#define B43_OFDMTAB_NOISESCALE B43_OFDMTAB(0x05, 0)
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#define B43_OFDMTAB_AGC2 B43_OFDMTAB(0x06, 0)
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#define B43_OFDMTAB_ROTOR B43_OFDMTAB(0x08, 0)
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#define B43_OFDMTAB_ADVRETARD B43_OFDMTAB(0x09, 0)
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#define B43_OFDMTAB_DAC B43_OFDMTAB(0x0C, 0)
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#define B43_OFDMTAB_DC B43_OFDMTAB(0x0E, 7)
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#define B43_OFDMTAB_PWRDYN2 B43_OFDMTAB(0x0E, 12)
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#define B43_OFDMTAB_LNAGAIN B43_OFDMTAB(0x0E, 13)
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#define B43_OFDMTAB_UNKNOWN_0F B43_OFDMTAB(0x0F, 0) //TODO rename
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#define B43_OFDMTAB_UNKNOWN_APHY B43_OFDMTAB(0x0F, 7) //TODO rename
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#define B43_OFDMTAB_LPFGAIN B43_OFDMTAB(0x0F, 12)
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#define B43_OFDMTAB_RSSI B43_OFDMTAB(0x10, 0)
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#define B43_OFDMTAB_UNKNOWN_11 B43_OFDMTAB(0x11, 4) //TODO rename
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#define B43_OFDMTAB_AGC1_R1 B43_OFDMTAB(0x13, 0)
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#define B43_OFDMTAB_GAINX_R1 B43_OFDMTAB(0x14, 0) //TODO remove!
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#define B43_OFDMTAB_MINSIGSQ B43_OFDMTAB(0x14, 0)
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#define B43_OFDMTAB_AGC3_R1 B43_OFDMTAB(0x15, 0)
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#define B43_OFDMTAB_WRSSI_R1 B43_OFDMTAB(0x15, 4)
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#define B43_OFDMTAB_TSSI B43_OFDMTAB(0x15, 0)
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#define B43_OFDMTAB_DACRFPABB B43_OFDMTAB(0x16, 0)
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#define B43_OFDMTAB_DACOFF B43_OFDMTAB(0x17, 0)
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#define B43_OFDMTAB_DCBIAS B43_OFDMTAB(0x18, 0)
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u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset);
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void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table,
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u16 offset, u16 value);
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u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset);
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void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table,
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u16 offset, u32 value);
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/*** G-PHY table numbers */
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#define B43_GTAB(number, offset) (((number) << B43_PHY_GTABNR_SHIFT) | (offset))
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#define B43_GTAB_NRSSI B43_GTAB(0x00, 0)
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#define B43_GTAB_TRFEMW B43_GTAB(0x0C, 0x120)
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#define B43_GTAB_ORIGTR B43_GTAB(0x2E, 0x298)
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u16 b43_gtab_read(struct b43_wldev *dev, u16 table, u16 offset); //TODO implement
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void b43_gtab_write(struct b43_wldev *dev, u16 table, u16 offset, u16 value); //TODO implement
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#define B43_DEFAULT_CHANNEL_A 36
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#define B43_DEFAULT_CHANNEL_BG 6
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enum {
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B43_ANTENNA0, /* Antenna 0 */
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B43_ANTENNA1, /* Antenna 0 */
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B43_ANTENNA_AUTO1, /* Automatic, starting with antenna 1 */
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B43_ANTENNA_AUTO0, /* Automatic, starting with antenna 0 */
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B43_ANTENNA2,
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B43_ANTENNA3 = 8,
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B43_ANTENNA_AUTO = B43_ANTENNA_AUTO0,
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B43_ANTENNA_DEFAULT = B43_ANTENNA_AUTO,
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};
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enum {
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B43_INTERFMODE_NONE,
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B43_INTERFMODE_NONWLAN,
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B43_INTERFMODE_MANUALWLAN,
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B43_INTERFMODE_AUTOWLAN,
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};
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/* Masks for the different PHY versioning registers. */
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#define B43_PHYVER_ANALOG 0xF000
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#define B43_PHYVER_ANALOG_SHIFT 12
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#define B43_PHYVER_TYPE 0x0F00
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#define B43_PHYVER_TYPE_SHIFT 8
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#define B43_PHYVER_VERSION 0x00FF
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void b43_phy_lock(struct b43_wldev *dev);
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void b43_phy_unlock(struct b43_wldev *dev);
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/* Read a value from a PHY register */
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u16 b43_phy_read(struct b43_wldev *dev, u16 offset);
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/* Write a value to a PHY register */
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void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val);
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/* Mask a PHY register with a mask */
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void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask);
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/* OR a PHY register with a bitmap */
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void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set);
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/* Mask and OR a PHY register with a mask and bitmap */
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void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set);
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int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev);
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void b43_phy_early_init(struct b43_wldev *dev);
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int b43_phy_init(struct b43_wldev *dev);
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void b43_set_rx_antenna(struct b43_wldev *dev, int antenna);
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void b43_phy_xmitpower(struct b43_wldev *dev);
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/* Returns the boolean whether the board has HardwarePowerControl */
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bool b43_has_hardware_pctl(struct b43_phy *phy);
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/* Returns the boolean whether "TX Magnification" is enabled. */
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#define has_tx_magnification(phy) \
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(((phy)->rev >= 2) && \
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((phy)->radio_ver == 0x2050) && \
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((phy)->radio_rev == 8))
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/* Card uses the loopback gain stuff */
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#define has_loopback_gain(phy) \
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(((phy)->rev > 1) || ((phy)->gmode))
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/* Radio Attenuation (RF Attenuation) */
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struct b43_rfatt {
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u8 att; /* Attenuation value */
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bool with_padmix; /* Flag, PAD Mixer enabled. */
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};
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struct b43_rfatt_list {
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/* Attenuation values list */
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const struct b43_rfatt *list;
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u8 len;
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/* Minimum/Maximum attenuation values */
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u8 min_val;
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u8 max_val;
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};
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/* Returns true, if the values are the same. */
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static inline bool b43_compare_rfatt(const struct b43_rfatt *a,
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const struct b43_rfatt *b)
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{
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return ((a->att == b->att) &&
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(a->with_padmix == b->with_padmix));
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}
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/* Baseband Attenuation */
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struct b43_bbatt {
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u8 att; /* Attenuation value */
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};
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struct b43_bbatt_list {
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/* Attenuation values list */
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const struct b43_bbatt *list;
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u8 len;
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/* Minimum/Maximum attenuation values */
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u8 min_val;
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u8 max_val;
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};
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/* Returns true, if the values are the same. */
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static inline bool b43_compare_bbatt(const struct b43_bbatt *a,
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const struct b43_bbatt *b)
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{
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return (a->att == b->att);
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}
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/* tx_control bits. */
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#define B43_TXCTL_PA3DB 0x40 /* PA Gain 3dB */
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#define B43_TXCTL_PA2DB 0x20 /* PA Gain 2dB */
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#define B43_TXCTL_TXMIX 0x10 /* TX Mixer Gain */
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/* Write BasebandAttenuation value to the device. */
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void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
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u16 baseband_attenuation);
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extern const u8 b43_radio_channel_codes_bg[];
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void b43_radio_lock(struct b43_wldev *dev);
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void b43_radio_unlock(struct b43_wldev *dev);
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/* Read a value from a 16bit radio register */
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u16 b43_radio_read16(struct b43_wldev *dev, u16 offset);
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/* Write a value to a 16bit radio register */
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void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val);
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/* Mask a 16bit radio register with a mask */
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void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask);
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/* OR a 16bit radio register with a bitmap */
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void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set);
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/* Mask and OR a PHY register with a mask and bitmap */
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void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set);
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u16 b43_radio_init2050(struct b43_wldev *dev);
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void b43_radio_init2060(struct b43_wldev *dev);
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void b43_radio_turn_on(struct b43_wldev *dev);
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void b43_radio_turn_off(struct b43_wldev *dev, bool force);
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int b43_radio_selectchannel(struct b43_wldev *dev, u8 channel,
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int synthetic_pu_workaround);
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u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel);
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u8 b43_radio_aci_scan(struct b43_wldev *dev);
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int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode);
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void b43_calc_nrssi_slope(struct b43_wldev *dev);
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void b43_calc_nrssi_threshold(struct b43_wldev *dev);
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s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset);
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void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val);
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void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val);
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void b43_nrssi_mem_update(struct b43_wldev *dev);
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void b43_radio_set_tx_iq(struct b43_wldev *dev);
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u16 b43_radio_calibrationvalue(struct b43_wldev *dev);
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void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
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int *_bbatt, int *_rfatt);
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void b43_set_txpower_g(struct b43_wldev *dev,
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const struct b43_bbatt *bbatt,
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const struct b43_rfatt *rfatt, u8 tx_control);
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#endif /* B43_PHY_H_ */
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