Paul Walmsley d0ba3922ae OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change ... Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley <paul@pwsan.com>		2009-06-19 19:09:31 -06:00
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mach	OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change	2009-06-19 19:09:31 -06:00