forked from Minki/linux
05bdabe7eb
This patch adds psci comatible properties to support all mandatory functions of PSCI-1.0, PSCI-0.2 and PSCI-0.1, and system suspend can be supported in PSCI-1.0. Signed-off-by: Fan Chen <fan.chen@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
576 lines
15 KiB
Plaintext
576 lines
15 KiB
Plaintext
/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Eddie Huang <eddie.huang@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/mt8173-power.h>
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#include <dt-bindings/reset-controller/mt8173-resets.h>
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#include "mt8173-pinfunc.h"
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/ {
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compatible = "mediatek,mt8173";
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interrupt-parent = <&sysirq>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu2>;
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};
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core1 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x000>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x001>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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};
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idle-states {
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entry-method = "psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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entry-latency-us = <639>;
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exit-latency-us = <680>;
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min-residency-us = <1088>;
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arm,psci-suspend-param = <0x0010000>;
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};
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};
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
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method = "smc";
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cpu_suspend = <0x84000001>;
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cpu_off = <0x84000002>;
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cpu_on = <0x84000003>;
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};
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clk26m: oscillator@0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "clk26m";
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};
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clk32k: oscillator@1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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clock-output-names = "clk32k";
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};
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cpum_ck: oscillator@2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "cpum_ck";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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topckgen: clock-controller@10000000 {
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compatible = "mediatek,mt8173-topckgen";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: power-controller@10001000 {
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compatible = "mediatek,mt8173-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pericfg: power-controller@10003000 {
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compatible = "mediatek,mt8173-pericfg", "syscon";
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reg = <0 0x10003000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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syscfg_pctl_a: syscfg_pctl_a@10005000 {
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compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
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reg = <0 0x10005000 0 0x1000>;
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};
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pio: pinctrl@0x10005000 {
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compatible = "mediatek,mt8173-pinctrl";
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reg = <0 0x1000b000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>;
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pins-are-numbered;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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i2c0_pins_a: i2c0 {
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pins1 {
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pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
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<MT8173_PIN_46_SCL0__FUNC_SCL0>;
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bias-disable;
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};
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};
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i2c1_pins_a: i2c1 {
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pins1 {
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pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
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<MT8173_PIN_126_SCL1__FUNC_SCL1>;
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bias-disable;
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};
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};
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i2c2_pins_a: i2c2 {
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pins1 {
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pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
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<MT8173_PIN_44_SCL2__FUNC_SCL2>;
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bias-disable;
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};
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};
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i2c3_pins_a: i2c3 {
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pins1 {
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pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
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<MT8173_PIN_107_SCL3__FUNC_SCL3>;
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bias-disable;
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};
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};
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i2c4_pins_a: i2c4 {
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pins1 {
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pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
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<MT8173_PIN_134_SCL4__FUNC_SCL4>;
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bias-disable;
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};
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};
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i2c6_pins_a: i2c6 {
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pins1 {
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pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
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<MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
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bias-disable;
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};
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};
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};
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scpsys: scpsys@10006000 {
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compatible = "mediatek,mt8173-scpsys";
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#power-domain-cells = <1>;
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reg = <0 0x10006000 0 0x1000>;
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clocks = <&clk26m>,
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<&topckgen CLK_TOP_MM_SEL>,
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<&topckgen CLK_TOP_VENC_SEL>,
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<&topckgen CLK_TOP_VENC_LT_SEL>;
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clock-names = "mfg", "mm", "venc", "venc_lt";
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infracfg = <&infracfg>;
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};
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watchdog: watchdog@10007000 {
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compatible = "mediatek,mt8173-wdt",
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"mediatek,mt6589-wdt";
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reg = <0 0x10007000 0 0x100>;
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};
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timer: timer@10008000 {
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compatible = "mediatek,mt8173-timer",
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"mediatek,mt6577-timer";
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reg = <0 0x10008000 0 0x1000>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_CLK_13M>,
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<&topckgen CLK_TOP_RTC_SEL>;
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};
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pwrap: pwrap@1000d000 {
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compatible = "mediatek,mt8173-pwrap";
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reg = <0 0x1000d000 0 0x1000>;
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reg-names = "pwrap";
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
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reset-names = "pwrap";
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clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
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clock-names = "spi", "wrap";
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};
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sysirq: intpol-controller@10200620 {
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compatible = "mediatek,mt8173-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10200620 0 0x20>;
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};
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apmixedsys: clock-controller@10209000 {
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compatible = "mediatek,mt8173-apmixedsys";
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reg = <0 0x10209000 0 0x1000>;
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#clock-cells = <1>;
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};
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gic: interrupt-controller@10220000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x10221000 0 0x1000>,
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<0 0x10222000 0 0x2000>,
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<0 0x10224000 0 0x2000>,
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<0 0x10226000 0 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt8173-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt8173-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt8173-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart3: serial@11005000 {
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compatible = "mediatek,mt8173-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11005000 0 0x400>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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i2c0: i2c@11007000 {
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compatible = "mediatek,mt8173-i2c";
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reg = <0 0x11007000 0 0x70>,
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<0 0x11000100 0 0x80>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C0>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins_a>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@11008000 {
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compatible = "mediatek,mt8173-i2c";
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reg = <0 0x11008000 0 0x70>,
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<0 0x11000180 0 0x80>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C1>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins_a>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@11009000 {
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compatible = "mediatek,mt8173-i2c";
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reg = <0 0x11009000 0 0x70>,
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<0 0x11000200 0 0x80>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C2>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_pins_a>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi: spi@1100a000 {
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compatible = "mediatek,mt8173-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x1100a000 0 0x1000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI_SEL>,
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<&pericfg CLK_PERI_SPI0>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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i2c3: i2c@11010000 {
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compatible = "mediatek,mt8173-i2c";
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reg = <0 0x11010000 0 0x70>,
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<0 0x11000280 0 0x80>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C3>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_pins_a>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c4: i2c@11011000 {
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compatible = "mediatek,mt8173-i2c";
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reg = <0 0x11011000 0 0x70>,
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<0 0x11000300 0 0x80>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C4>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_pins_a>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c6: i2c@11013000 {
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compatible = "mediatek,mt8173-i2c";
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reg = <0 0x11013000 0 0x70>,
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<0 0x11000080 0 0x80>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C6>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c6_pins_a>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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afe: audio-controller@11220000 {
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compatible = "mediatek,mt8173-afe-pcm";
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reg = <0 0x11220000 0 0x1000>;
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interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
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clocks = <&infracfg CLK_INFRA_AUDIO>,
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<&topckgen CLK_TOP_AUDIO_SEL>,
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<&topckgen CLK_TOP_AUD_INTBUS_SEL>,
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<&topckgen CLK_TOP_APLL1_DIV0>,
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<&topckgen CLK_TOP_APLL2_DIV0>,
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<&topckgen CLK_TOP_I2S0_M_SEL>,
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<&topckgen CLK_TOP_I2S1_M_SEL>,
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<&topckgen CLK_TOP_I2S2_M_SEL>,
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<&topckgen CLK_TOP_I2S3_M_SEL>,
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<&topckgen CLK_TOP_I2S3_B_SEL>;
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clock-names = "infra_sys_audio_clk",
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"top_pdn_audio",
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"top_pdn_aud_intbus",
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"bck0",
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"bck1",
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"i2s0_m",
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"i2s1_m",
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"i2s2_m",
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"i2s3_m",
|
|
"i2s3_b";
|
|
assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
|
|
<&topckgen CLK_TOP_AUD_2_SEL>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
|
|
<&topckgen CLK_TOP_APLL2>;
|
|
};
|
|
|
|
mmc0: mmc@11230000 {
|
|
compatible = "mediatek,mt8173-mmc",
|
|
"mediatek,mt8135-mmc";
|
|
reg = <0 0x11230000 0 0x1000>;
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_MSDC30_0>,
|
|
<&topckgen CLK_TOP_MSDC50_0_H_SEL>;
|
|
clock-names = "source", "hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc1: mmc@11240000 {
|
|
compatible = "mediatek,mt8173-mmc",
|
|
"mediatek,mt8135-mmc";
|
|
reg = <0 0x11240000 0 0x1000>;
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_MSDC30_1>,
|
|
<&topckgen CLK_TOP_AXI_SEL>;
|
|
clock-names = "source", "hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc2: mmc@11250000 {
|
|
compatible = "mediatek,mt8173-mmc",
|
|
"mediatek,mt8135-mmc";
|
|
reg = <0 0x11250000 0 0x1000>;
|
|
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_MSDC30_2>,
|
|
<&topckgen CLK_TOP_AXI_SEL>;
|
|
clock-names = "source", "hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc3: mmc@11260000 {
|
|
compatible = "mediatek,mt8173-mmc",
|
|
"mediatek,mt8135-mmc";
|
|
reg = <0 0x11260000 0 0x1000>;
|
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_MSDC30_3>,
|
|
<&topckgen CLK_TOP_MSDC50_2_H_SEL>;
|
|
clock-names = "source", "hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmsys: clock-controller@14000000 {
|
|
compatible = "mediatek,mt8173-mmsys", "syscon";
|
|
reg = <0 0x14000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
pwm0: pwm@1401e000 {
|
|
compatible = "mediatek,mt8173-disp-pwm",
|
|
"mediatek,mt6595-disp-pwm";
|
|
reg = <0 0x1401e000 0 0x1000>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&mmsys CLK_MM_DISP_PWM026M>,
|
|
<&mmsys CLK_MM_DISP_PWM0MM>;
|
|
clock-names = "main", "mm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@1401f000 {
|
|
compatible = "mediatek,mt8173-disp-pwm",
|
|
"mediatek,mt6595-disp-pwm";
|
|
reg = <0 0x1401f000 0 0x1000>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&mmsys CLK_MM_DISP_PWM126M>,
|
|
<&mmsys CLK_MM_DISP_PWM1MM>;
|
|
clock-names = "main", "mm";
|
|
status = "disabled";
|
|
};
|
|
|
|
imgsys: clock-controller@15000000 {
|
|
compatible = "mediatek,mt8173-imgsys", "syscon";
|
|
reg = <0 0x15000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
vdecsys: clock-controller@16000000 {
|
|
compatible = "mediatek,mt8173-vdecsys", "syscon";
|
|
reg = <0 0x16000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
vencsys: clock-controller@18000000 {
|
|
compatible = "mediatek,mt8173-vencsys", "syscon";
|
|
reg = <0 0x18000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
vencltsys: clock-controller@19000000 {
|
|
compatible = "mediatek,mt8173-vencltsys", "syscon";
|
|
reg = <0 0x19000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
};
|
|
};
|
|
|