e82b5fe5d4
* Use one compatible line per line in the documentation
* Remove SoC revision depended compatible lines, we can detect that in
the driver
* Use lower case letters in hex addresses
* Fix the size of the address ranges in the example, this now matches
the sizes used by the SoC. The old ones will also work, this just adds
some empty address space.
* Change the reg size of the gphy-fw node
Fixes: 86ce2bc73c ("dt-bindings: net: dsa: Add lantiq, xrx200-gswip DT bindings")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: devicetree@vger.kernel.org
Signed-off-by: David S. Miller <davem@davemloft.net>
144 lines
2.8 KiB
Plaintext
144 lines
2.8 KiB
Plaintext
Lantiq GSWIP Ethernet switches
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==================================
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Required properties for GSWIP core:
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- compatible : "lantiq,xrx200-gswip" for the embedded GSWIP in the
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xRX200 SoC
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- reg : memory range of the GSWIP core registers
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: memory range of the GSWIP MDIO registers
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: memory range of the GSWIP MII registers
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See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of
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additional required and optional properties.
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Required properties for MDIO bus:
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- compatible : "lantiq,xrx200-mdio" for the MDIO bus inside the GSWIP
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core of the xRX200 SoC and the PHYs connected to it.
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See Documentation/devicetree/bindings/net/mdio.txt for a list of additional
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required and optional properties.
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Required properties for GPHY firmware loading:
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- compatible : "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw"
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"lantiq,xrx300-gphy-fw", "lantiq,gphy-fw"
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"lantiq,xrx330-gphy-fw", "lantiq,gphy-fw"
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for the loading of the firmware into the embedded
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GPHY core of the SoC.
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- lantiq,rcu : reference to the rcu syscon
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The GPHY firmware loader has a list of GPHY entries, one for each
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embedded GPHY
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- reg : Offset of the GPHY firmware register in the RCU
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register range
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- resets : list of resets of the embedded GPHY
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- reset-names : list of names of the resets
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Example:
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Ethernet switch on the VRX200 SoC:
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switch@e108000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-gswip";
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reg = < 0xe108000 0x3100 /* switch */
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0xe10b100 0xd8 /* mdio */
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0xe10b1d8 0x130 /* mii */
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>;
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dsa,member = <0 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan3";
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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};
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port@1 {
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reg = <1>;
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label = "lan4";
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-mode = "internal";
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phy-handle = <&phy11>;
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};
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port@4 {
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reg = <4>;
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label = "lan1";
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phy-mode = "internal";
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phy-handle = <&phy13>;
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};
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port@5 {
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reg = <5>;
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label = "wan";
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phy-mode = "rgmii";
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phy-handle = <&phy5>;
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};
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port@6 {
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reg = <0x6>;
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label = "cpu";
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ethernet = <ð0>;
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-mdio";
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reg = <0>;
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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phy5: ethernet-phy@5 {
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reg = <0x5>;
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};
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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};
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phy13: ethernet-phy@13 {
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reg = <0x13>;
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};
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};
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gphy-fw {
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compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
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lantiq,rcu = <&rcu0>;
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#address-cells = <1>;
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#size-cells = <0>;
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gphy@20 {
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reg = <0x20>;
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resets = <&reset0 31 30>;
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reset-names = "gphy";
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};
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gphy@68 {
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reg = <0x68>;
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resets = <&reset0 29 28>;
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reset-names = "gphy";
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};
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};
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};
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