forked from Minki/linux
cfc5604c48
This patch changes the prototype of spi_nor_scan(): its 3rd parameter is replaced by a 'struct spi_nor_hwcaps' pointer, which tells the spi-nor framework about the actual hardware capabilities supported by the SPI controller and its driver. Besides, this patch also introduces a new 'struct spi_nor_flash_parameter' telling the spi-nor framework about the hardware capabilities supported by the SPI flash memory and the associated settings required to use those hardware caps. Then, to improve the readability of spi_nor_scan(), the discovery of the memory settings and the memory initialization are now split into two dedicated functions. 1 - spi_nor_init_params() The spi_nor_init_params() function is responsible for initializing the 'struct spi_nor_flash_parameter'. Currently this structure is filled with legacy values but further patches will allow to override some parameter values dynamically, for instance by reading the JESD216 Serial Flash Discoverable Parameter (SFDP) tables from the SPI memory. The spi_nor_init_params() function only deals with the hardware capabilities of the SPI flash memory: especially it doesn't care about the hardware capabilities supported by the SPI controller. 2 - spi_nor_setup() The second function is called once the 'struct spi_nor_flash_parameter' has been initialized by spi_nor_init_params(). With both 'struct spi_nor_flash_parameter' and 'struct spi_nor_hwcaps', the new argument of spi_nor_scan(), spi_nor_setup() computes the best match between hardware caps supported by both the (Q)SPI memory and controller hence selecting the relevant settings for (Fast) Read and Page Program operations. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
2026 lines
57 KiB
C
2026 lines
57 KiB
C
/*
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* Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
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* influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
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*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*
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* This code is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/mutex.h>
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#include <linux/math64.h>
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#include <linux/sizes.h>
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#include <linux/mtd/mtd.h>
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#include <linux/of_platform.h>
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#include <linux/spi/flash.h>
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#include <linux/mtd/spi-nor.h>
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/* Define max times to check status register before we give up. */
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/*
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* For everything but full-chip erase; probably could be much smaller, but kept
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* around for safety for now
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*/
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#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
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/*
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* For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
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* for larger flash
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*/
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#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
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#define SPI_NOR_MAX_ID_LEN 6
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#define SPI_NOR_MAX_ADDR_WIDTH 4
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struct flash_info {
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char *name;
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/*
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* This array stores the ID bytes.
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* The first three bytes are the JEDIC ID.
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* JEDEC ID zero means "no ID" (mostly older chips).
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*/
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u8 id[SPI_NOR_MAX_ID_LEN];
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u8 id_len;
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/* The size listed here is what works with SPINOR_OP_SE, which isn't
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* necessarily called a "sector" by the vendor.
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*/
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unsigned sector_size;
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u16 n_sectors;
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u16 page_size;
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u16 addr_width;
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u16 flags;
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#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
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#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
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#define SST_WRITE BIT(2) /* use SST byte programming */
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#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
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#define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
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#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
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#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
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#define USE_FSR BIT(7) /* use flag status register */
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#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
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#define SPI_NOR_HAS_TB BIT(9) /*
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* Flash SR has Top/Bottom (TB) protect
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* bit. Must be used with
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* SPI_NOR_HAS_LOCK.
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*/
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#define SPI_S3AN BIT(10) /*
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* Xilinx Spartan 3AN In-System Flash
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* (MFR cannot be used for probing
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* because it has the same value as
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* ATMEL flashes)
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*/
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#define SPI_NOR_4B_OPCODES BIT(11) /*
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* Use dedicated 4byte address op codes
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* to support memory size above 128Mib.
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*/
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#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
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};
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#define JEDEC_MFR(info) ((info)->id[0])
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static const struct flash_info *spi_nor_match_id(const char *name);
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/*
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* Read the status register, returning its value in the location
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* Return the status register value.
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* Returns negative if error occurred.
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*/
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static int read_sr(struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
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if (ret < 0) {
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pr_err("error %d reading SR\n", (int) ret);
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return ret;
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}
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return val;
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}
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/*
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* Read the flag status register, returning its value in the location
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* Return the status register value.
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* Returns negative if error occurred.
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*/
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static int read_fsr(struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
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if (ret < 0) {
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pr_err("error %d reading FSR\n", ret);
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return ret;
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}
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return val;
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}
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/*
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* Read configuration register, returning its value in the
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* location. Return the configuration register value.
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* Returns negative if error occurred.
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*/
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static int read_cr(struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
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if (ret < 0) {
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dev_err(nor->dev, "error %d reading CR\n", ret);
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return ret;
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}
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return val;
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}
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/*
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* Write status register 1 byte
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* Returns negative if error occurred.
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*/
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static inline int write_sr(struct spi_nor *nor, u8 val)
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{
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nor->cmd_buf[0] = val;
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return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
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}
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/*
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* Set write enable latch with Write Enable command.
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* Returns negative if error occurred.
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*/
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static inline int write_enable(struct spi_nor *nor)
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{
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return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
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}
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/*
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* Send write disable instruction to the chip.
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*/
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static inline int write_disable(struct spi_nor *nor)
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{
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return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
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}
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static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
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{
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return mtd->priv;
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}
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static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
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{
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size_t i;
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for (i = 0; i < size; i++)
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if (table[i][0] == opcode)
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return table[i][1];
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/* No conversion found, keep input op code. */
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return opcode;
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}
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static inline u8 spi_nor_convert_3to4_read(u8 opcode)
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{
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static const u8 spi_nor_3to4_read[][2] = {
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{ SPINOR_OP_READ, SPINOR_OP_READ_4B },
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{ SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
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{ SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
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{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
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{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
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{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
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};
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return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
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ARRAY_SIZE(spi_nor_3to4_read));
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}
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static inline u8 spi_nor_convert_3to4_program(u8 opcode)
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{
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static const u8 spi_nor_3to4_program[][2] = {
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{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
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{ SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
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{ SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
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};
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return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
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ARRAY_SIZE(spi_nor_3to4_program));
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}
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static inline u8 spi_nor_convert_3to4_erase(u8 opcode)
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{
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static const u8 spi_nor_3to4_erase[][2] = {
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{ SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
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{ SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
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{ SPINOR_OP_SE, SPINOR_OP_SE_4B },
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};
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return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
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ARRAY_SIZE(spi_nor_3to4_erase));
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}
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static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
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const struct flash_info *info)
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{
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/* Do some manufacturer fixups first */
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switch (JEDEC_MFR(info)) {
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case SNOR_MFR_SPANSION:
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/* No small sector erase for 4-byte command set */
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nor->erase_opcode = SPINOR_OP_SE;
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nor->mtd.erasesize = info->sector_size;
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break;
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default:
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break;
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}
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nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
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nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
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nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
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}
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/* Enable/disable 4-byte addressing mode. */
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static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
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int enable)
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{
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int status;
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bool need_wren = false;
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u8 cmd;
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switch (JEDEC_MFR(info)) {
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case SNOR_MFR_MICRON:
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/* Some Micron need WREN command; all will accept it */
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need_wren = true;
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case SNOR_MFR_MACRONIX:
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case SNOR_MFR_WINBOND:
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if (need_wren)
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write_enable(nor);
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cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
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status = nor->write_reg(nor, cmd, NULL, 0);
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if (need_wren)
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write_disable(nor);
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return status;
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default:
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/* Spansion style */
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nor->cmd_buf[0] = enable << 7;
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return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
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}
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}
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static int s3an_sr_ready(struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
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if (ret < 0) {
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dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
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return ret;
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}
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return !!(val & XSR_RDY);
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}
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static inline int spi_nor_sr_ready(struct spi_nor *nor)
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{
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int sr = read_sr(nor);
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if (sr < 0)
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return sr;
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else
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return !(sr & SR_WIP);
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}
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static inline int spi_nor_fsr_ready(struct spi_nor *nor)
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{
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int fsr = read_fsr(nor);
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if (fsr < 0)
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return fsr;
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else
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return fsr & FSR_READY;
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}
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static int spi_nor_ready(struct spi_nor *nor)
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{
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int sr, fsr;
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if (nor->flags & SNOR_F_READY_XSR_RDY)
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sr = s3an_sr_ready(nor);
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else
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sr = spi_nor_sr_ready(nor);
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if (sr < 0)
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return sr;
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fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
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if (fsr < 0)
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return fsr;
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return sr && fsr;
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}
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/*
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* Service routine to read status register until ready, or timeout occurs.
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* Returns non-zero if error.
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*/
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static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
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unsigned long timeout_jiffies)
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{
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unsigned long deadline;
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int timeout = 0, ret;
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deadline = jiffies + timeout_jiffies;
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while (!timeout) {
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if (time_after_eq(jiffies, deadline))
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timeout = 1;
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ret = spi_nor_ready(nor);
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if (ret < 0)
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return ret;
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if (ret)
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return 0;
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cond_resched();
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}
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dev_err(nor->dev, "flash operation timed out\n");
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return -ETIMEDOUT;
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}
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static int spi_nor_wait_till_ready(struct spi_nor *nor)
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{
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return spi_nor_wait_till_ready_with_timeout(nor,
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DEFAULT_READY_WAIT_JIFFIES);
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}
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/*
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* Erase the whole flash memory
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*
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* Returns 0 if successful, non-zero otherwise.
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*/
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static int erase_chip(struct spi_nor *nor)
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{
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dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
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return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
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}
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static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
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{
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int ret = 0;
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mutex_lock(&nor->lock);
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if (nor->prepare) {
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ret = nor->prepare(nor, ops);
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if (ret) {
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dev_err(nor->dev, "failed in the preparation.\n");
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mutex_unlock(&nor->lock);
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return ret;
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}
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}
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return ret;
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}
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static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
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{
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if (nor->unprepare)
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nor->unprepare(nor, ops);
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mutex_unlock(&nor->lock);
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}
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/*
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* This code converts an address to the Default Address Mode, that has non
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* power of two page sizes. We must support this mode because it is the default
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* mode supported by Xilinx tools, it can access the whole flash area and
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* changing over to the Power-of-two mode is irreversible and corrupts the
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* original data.
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* Addr can safely be unsigned int, the biggest S3AN device is smaller than
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* 4 MiB.
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*/
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static loff_t spi_nor_s3an_addr_convert(struct spi_nor *nor, unsigned int addr)
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{
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unsigned int offset;
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unsigned int page;
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offset = addr % nor->page_size;
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page = addr / nor->page_size;
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page <<= (nor->page_size > 512) ? 10 : 9;
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return page | offset;
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}
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/*
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* Initiate the erasure of a single sector
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*/
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static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
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{
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u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
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int i;
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if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
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addr = spi_nor_s3an_addr_convert(nor, addr);
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if (nor->erase)
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return nor->erase(nor, addr);
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/*
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* Default implementation, if driver doesn't have a specialized HW
|
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* control
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*/
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for (i = nor->addr_width - 1; i >= 0; i--) {
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buf[i] = addr & 0xff;
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addr >>= 8;
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}
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return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
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}
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|
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/*
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* Erase an address range on the nor chip. The address range may extend
|
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* one or more erase sectors. Return an error is there is a problem erasing.
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*/
|
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static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
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{
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struct spi_nor *nor = mtd_to_spi_nor(mtd);
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u32 addr, len;
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uint32_t rem;
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int ret;
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dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
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(long long)instr->len);
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div_u64_rem(instr->len, mtd->erasesize, &rem);
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if (rem)
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return -EINVAL;
|
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|
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addr = instr->addr;
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len = instr->len;
|
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|
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ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
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if (ret)
|
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return ret;
|
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|
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/* whole-chip erase? */
|
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if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
|
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unsigned long timeout;
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|
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write_enable(nor);
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|
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if (erase_chip(nor)) {
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ret = -EIO;
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goto erase_err;
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}
|
|
|
|
/*
|
|
* Scale the timeout linearly with the size of the flash, with
|
|
* a minimum calibrated to an old 2MB flash. We could try to
|
|
* pull these from CFI/SFDP, but these values should be good
|
|
* enough for now.
|
|
*/
|
|
timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
|
|
CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
|
|
(unsigned long)(mtd->size / SZ_2M));
|
|
ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
|
|
if (ret)
|
|
goto erase_err;
|
|
|
|
/* REVISIT in some cases we could speed up erasing large regions
|
|
* by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
|
|
* to use "small sector erase", but that's not always optimal.
|
|
*/
|
|
|
|
/* "sector"-at-a-time erase */
|
|
} else {
|
|
while (len) {
|
|
write_enable(nor);
|
|
|
|
ret = spi_nor_erase_sector(nor, addr);
|
|
if (ret)
|
|
goto erase_err;
|
|
|
|
addr += mtd->erasesize;
|
|
len -= mtd->erasesize;
|
|
|
|
ret = spi_nor_wait_till_ready(nor);
|
|
if (ret)
|
|
goto erase_err;
|
|
}
|
|
}
|
|
|
|
write_disable(nor);
|
|
|
|
erase_err:
|
|
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
|
|
|
|
instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE;
|
|
mtd_erase_callback(instr);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
|
|
uint64_t *len)
|
|
{
|
|
struct mtd_info *mtd = &nor->mtd;
|
|
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
|
|
int shift = ffs(mask) - 1;
|
|
int pow;
|
|
|
|
if (!(sr & mask)) {
|
|
/* No protection */
|
|
*ofs = 0;
|
|
*len = 0;
|
|
} else {
|
|
pow = ((sr & mask) ^ mask) >> shift;
|
|
*len = mtd->size >> pow;
|
|
if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
|
|
*ofs = 0;
|
|
else
|
|
*ofs = mtd->size - *len;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Return 1 if the entire region is locked (if @locked is true) or unlocked (if
|
|
* @locked is false); 0 otherwise
|
|
*/
|
|
static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
|
|
u8 sr, bool locked)
|
|
{
|
|
loff_t lock_offs;
|
|
uint64_t lock_len;
|
|
|
|
if (!len)
|
|
return 1;
|
|
|
|
stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
|
|
|
|
if (locked)
|
|
/* Requested range is a sub-range of locked range */
|
|
return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
|
|
else
|
|
/* Requested range does not overlap with locked range */
|
|
return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
|
|
}
|
|
|
|
static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
|
|
u8 sr)
|
|
{
|
|
return stm_check_lock_status_sr(nor, ofs, len, sr, true);
|
|
}
|
|
|
|
static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
|
|
u8 sr)
|
|
{
|
|
return stm_check_lock_status_sr(nor, ofs, len, sr, false);
|
|
}
|
|
|
|
/*
|
|
* Lock a region of the flash. Compatible with ST Micro and similar flash.
|
|
* Supports the block protection bits BP{0,1,2} in the status register
|
|
* (SR). Does not support these features found in newer SR bitfields:
|
|
* - SEC: sector/block protect - only handle SEC=0 (block protect)
|
|
* - CMP: complement protect - only support CMP=0 (range is not complemented)
|
|
*
|
|
* Support for the following is provided conditionally for some flash:
|
|
* - TB: top/bottom protect
|
|
*
|
|
* Sample table portion for 8MB flash (Winbond w25q64fw):
|
|
*
|
|
* SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
|
|
* --------------------------------------------------------------------------
|
|
* X | X | 0 | 0 | 0 | NONE | NONE
|
|
* 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
|
|
* 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
|
|
* 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
|
|
* 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
|
|
* 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
|
|
* 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
|
|
* X | X | 1 | 1 | 1 | 8 MB | ALL
|
|
* ------|-------|-------|-------|-------|---------------|-------------------
|
|
* 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
|
|
* 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
|
|
* 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
|
|
* 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
|
|
* 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
|
|
* 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
|
|
*
|
|
* Returns negative on errors, 0 on success.
|
|
*/
|
|
static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
|
|
{
|
|
struct mtd_info *mtd = &nor->mtd;
|
|
int status_old, status_new;
|
|
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
|
|
u8 shift = ffs(mask) - 1, pow, val;
|
|
loff_t lock_len;
|
|
bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
|
|
bool use_top;
|
|
int ret;
|
|
|
|
status_old = read_sr(nor);
|
|
if (status_old < 0)
|
|
return status_old;
|
|
|
|
/* If nothing in our range is unlocked, we don't need to do anything */
|
|
if (stm_is_locked_sr(nor, ofs, len, status_old))
|
|
return 0;
|
|
|
|
/* If anything below us is unlocked, we can't use 'bottom' protection */
|
|
if (!stm_is_locked_sr(nor, 0, ofs, status_old))
|
|
can_be_bottom = false;
|
|
|
|
/* If anything above us is unlocked, we can't use 'top' protection */
|
|
if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
|
|
status_old))
|
|
can_be_top = false;
|
|
|
|
if (!can_be_bottom && !can_be_top)
|
|
return -EINVAL;
|
|
|
|
/* Prefer top, if both are valid */
|
|
use_top = can_be_top;
|
|
|
|
/* lock_len: length of region that should end up locked */
|
|
if (use_top)
|
|
lock_len = mtd->size - ofs;
|
|
else
|
|
lock_len = ofs + len;
|
|
|
|
/*
|
|
* Need smallest pow such that:
|
|
*
|
|
* 1 / (2^pow) <= (len / size)
|
|
*
|
|
* so (assuming power-of-2 size) we do:
|
|
*
|
|
* pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
|
|
*/
|
|
pow = ilog2(mtd->size) - ilog2(lock_len);
|
|
val = mask - (pow << shift);
|
|
if (val & ~mask)
|
|
return -EINVAL;
|
|
/* Don't "lock" with no region! */
|
|
if (!(val & mask))
|
|
return -EINVAL;
|
|
|
|
status_new = (status_old & ~mask & ~SR_TB) | val;
|
|
|
|
/* Disallow further writes if WP pin is asserted */
|
|
status_new |= SR_SRWD;
|
|
|
|
if (!use_top)
|
|
status_new |= SR_TB;
|
|
|
|
/* Don't bother if they're the same */
|
|
if (status_new == status_old)
|
|
return 0;
|
|
|
|
/* Only modify protection if it will not unlock other areas */
|
|
if ((status_new & mask) < (status_old & mask))
|
|
return -EINVAL;
|
|
|
|
write_enable(nor);
|
|
ret = write_sr(nor, status_new);
|
|
if (ret)
|
|
return ret;
|
|
return spi_nor_wait_till_ready(nor);
|
|
}
|
|
|
|
/*
|
|
* Unlock a region of the flash. See stm_lock() for more info
|
|
*
|
|
* Returns negative on errors, 0 on success.
|
|
*/
|
|
static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
|
|
{
|
|
struct mtd_info *mtd = &nor->mtd;
|
|
int status_old, status_new;
|
|
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
|
|
u8 shift = ffs(mask) - 1, pow, val;
|
|
loff_t lock_len;
|
|
bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
|
|
bool use_top;
|
|
int ret;
|
|
|
|
status_old = read_sr(nor);
|
|
if (status_old < 0)
|
|
return status_old;
|
|
|
|
/* If nothing in our range is locked, we don't need to do anything */
|
|
if (stm_is_unlocked_sr(nor, ofs, len, status_old))
|
|
return 0;
|
|
|
|
/* If anything below us is locked, we can't use 'top' protection */
|
|
if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
|
|
can_be_top = false;
|
|
|
|
/* If anything above us is locked, we can't use 'bottom' protection */
|
|
if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
|
|
status_old))
|
|
can_be_bottom = false;
|
|
|
|
if (!can_be_bottom && !can_be_top)
|
|
return -EINVAL;
|
|
|
|
/* Prefer top, if both are valid */
|
|
use_top = can_be_top;
|
|
|
|
/* lock_len: length of region that should remain locked */
|
|
if (use_top)
|
|
lock_len = mtd->size - (ofs + len);
|
|
else
|
|
lock_len = ofs;
|
|
|
|
/*
|
|
* Need largest pow such that:
|
|
*
|
|
* 1 / (2^pow) >= (len / size)
|
|
*
|
|
* so (assuming power-of-2 size) we do:
|
|
*
|
|
* pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
|
|
*/
|
|
pow = ilog2(mtd->size) - order_base_2(lock_len);
|
|
if (lock_len == 0) {
|
|
val = 0; /* fully unlocked */
|
|
} else {
|
|
val = mask - (pow << shift);
|
|
/* Some power-of-two sizes are not supported */
|
|
if (val & ~mask)
|
|
return -EINVAL;
|
|
}
|
|
|
|
status_new = (status_old & ~mask & ~SR_TB) | val;
|
|
|
|
/* Don't protect status register if we're fully unlocked */
|
|
if (lock_len == 0)
|
|
status_new &= ~SR_SRWD;
|
|
|
|
if (!use_top)
|
|
status_new |= SR_TB;
|
|
|
|
/* Don't bother if they're the same */
|
|
if (status_new == status_old)
|
|
return 0;
|
|
|
|
/* Only modify protection if it will not lock other areas */
|
|
if ((status_new & mask) > (status_old & mask))
|
|
return -EINVAL;
|
|
|
|
write_enable(nor);
|
|
ret = write_sr(nor, status_new);
|
|
if (ret)
|
|
return ret;
|
|
return spi_nor_wait_till_ready(nor);
|
|
}
|
|
|
|
/*
|
|
* Check if a region of the flash is (completely) locked. See stm_lock() for
|
|
* more info.
|
|
*
|
|
* Returns 1 if entire region is locked, 0 if any portion is unlocked, and
|
|
* negative on errors.
|
|
*/
|
|
static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
|
|
{
|
|
int status;
|
|
|
|
status = read_sr(nor);
|
|
if (status < 0)
|
|
return status;
|
|
|
|
return stm_is_locked_sr(nor, ofs, len, status);
|
|
}
|
|
|
|
static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
|
|
{
|
|
struct spi_nor *nor = mtd_to_spi_nor(mtd);
|
|
int ret;
|
|
|
|
ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nor->flash_lock(nor, ofs, len);
|
|
|
|
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
|
|
return ret;
|
|
}
|
|
|
|
static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
|
|
{
|
|
struct spi_nor *nor = mtd_to_spi_nor(mtd);
|
|
int ret;
|
|
|
|
ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nor->flash_unlock(nor, ofs, len);
|
|
|
|
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
|
|
return ret;
|
|
}
|
|
|
|
static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
|
|
{
|
|
struct spi_nor *nor = mtd_to_spi_nor(mtd);
|
|
int ret;
|
|
|
|
ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nor->flash_is_locked(nor, ofs, len);
|
|
|
|
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
|
|
return ret;
|
|
}
|
|
|
|
/* Used when the "_ext_id" is two bytes at most */
|
|
#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
|
|
.id = { \
|
|
((_jedec_id) >> 16) & 0xff, \
|
|
((_jedec_id) >> 8) & 0xff, \
|
|
(_jedec_id) & 0xff, \
|
|
((_ext_id) >> 8) & 0xff, \
|
|
(_ext_id) & 0xff, \
|
|
}, \
|
|
.id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
|
|
.sector_size = (_sector_size), \
|
|
.n_sectors = (_n_sectors), \
|
|
.page_size = 256, \
|
|
.flags = (_flags),
|
|
|
|
#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
|
|
.id = { \
|
|
((_jedec_id) >> 16) & 0xff, \
|
|
((_jedec_id) >> 8) & 0xff, \
|
|
(_jedec_id) & 0xff, \
|
|
((_ext_id) >> 16) & 0xff, \
|
|
((_ext_id) >> 8) & 0xff, \
|
|
(_ext_id) & 0xff, \
|
|
}, \
|
|
.id_len = 6, \
|
|
.sector_size = (_sector_size), \
|
|
.n_sectors = (_n_sectors), \
|
|
.page_size = 256, \
|
|
.flags = (_flags),
|
|
|
|
#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
|
|
.sector_size = (_sector_size), \
|
|
.n_sectors = (_n_sectors), \
|
|
.page_size = (_page_size), \
|
|
.addr_width = (_addr_width), \
|
|
.flags = (_flags),
|
|
|
|
#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
|
|
.id = { \
|
|
((_jedec_id) >> 16) & 0xff, \
|
|
((_jedec_id) >> 8) & 0xff, \
|
|
(_jedec_id) & 0xff \
|
|
}, \
|
|
.id_len = 3, \
|
|
.sector_size = (8*_page_size), \
|
|
.n_sectors = (_n_sectors), \
|
|
.page_size = _page_size, \
|
|
.addr_width = 3, \
|
|
.flags = SPI_NOR_NO_FR | SPI_S3AN,
|
|
|
|
/* NOTE: double check command sets and memory organization when you add
|
|
* more nor chips. This current list focusses on newer chips, which
|
|
* have been converging on command sets which including JEDEC ID.
|
|
*
|
|
* All newly added entries should describe *hardware* and should use SECT_4K
|
|
* (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
|
|
* scenarios excluding small sectors there is config option that can be
|
|
* disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
|
|
* For historical (and compatibility) reasons (before we got above config) some
|
|
* old entries may be missing 4K flag.
|
|
*/
|
|
static const struct flash_info spi_nor_ids[] = {
|
|
/* Atmel -- some are (confusingly) marketed as "DataFlash" */
|
|
{ "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
|
|
{ "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
|
|
|
|
{ "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
|
|
{ "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
|
|
|
|
{ "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
|
|
{ "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
|
|
{ "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
|
|
{ "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
|
|
|
|
{ "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
|
|
|
|
/* EON -- en25xxx */
|
|
{ "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
|
|
{ "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
|
|
{ "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
|
|
{ "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
|
|
{ "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
|
|
{ "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
|
|
{ "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
|
|
|
|
/* ESMT */
|
|
{ "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
|
|
{ "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
|
|
{ "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
|
|
|
|
/* Everspin */
|
|
{ "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
|
|
{ "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
|
|
{ "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
|
|
|
|
/* Fujitsu */
|
|
{ "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
|
|
|
|
/* GigaDevice */
|
|
{
|
|
"gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
|
|
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
|
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
|
|
},
|
|
{
|
|
"gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
|
|
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
|
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
|
|
},
|
|
{
|
|
"gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
|
|
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
|
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
|
|
},
|
|
{
|
|
"gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
|
|
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
|
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
|
|
},
|
|
{
|
|
"gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
|
|
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
|
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
|
|
},
|
|
|
|
/* Intel/Numonyx -- xxxs33b */
|
|
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
|
|
{ "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
|
|
{ "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
|
|
|
|
/* ISSI */
|
|
{ "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
|
|
|
|
/* Macronix */
|
|
{ "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
|
|
{ "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
|
|
{ "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
|
|
{ "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
|
|
{ "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
|
|
{ "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
|
|
{ "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
|
|
{ "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
|
|
{ "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
|
|
{ "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
|
|
{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
|
|
{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
|
|
{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
|
|
{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
|
|
{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
|
|
{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
|
|
{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
|
|
|
|
/* Micron */
|
|
{ "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
|
|
{ "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
|
|
{ "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
|
|
{ "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
|
|
{ "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
|
|
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
|
|
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
|
|
{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
|
|
{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
|
|
{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
|
|
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
|
|
{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
|
|
{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
|
|
|
|
/* PMC */
|
|
{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
|
|
{ "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
|
|
{ "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
|
|
|
|
/* Spansion -- single (large) sector size only, at least
|
|
* for the chips listed here (without boot sectors).
|
|
*/
|
|
{ "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
|
|
{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
|
|
{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
|
|
{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
|
|
{ "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
|
|
{ "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
|
|
{ "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
|
|
{ "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
|
|
{ "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
|
|
{ "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
|
|
{ "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
|
|
{ "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
|
|
{ "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
|
|
|
|
/* SST -- large erase sizes are "overlays", "sectors" are 4K */
|
|
{ "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
|
|
{ "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
|
|
{ "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
|
|
{ "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
|
|
{ "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
|
|
{ "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
|
|
{ "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
|
|
{ "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
|
|
{ "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
|
|
{ "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
|
|
{ "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
|
|
{ "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
|
|
|
|
/* ST Microelectronics -- newer production may have feature updates */
|
|
{ "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
|
|
{ "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
|
|
{ "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
|
|
{ "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
|
|
{ "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
|
|
{ "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
|
|
{ "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
|
|
{ "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
|
|
{ "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
|
|
|
|
{ "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
|
|
{ "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
|
|
{ "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
|
|
{ "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
|
|
{ "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
|
|
{ "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
|
|
{ "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
|
|
{ "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
|
|
{ "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
|
|
|
|
{ "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
|
|
{ "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
|
|
{ "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
|
|
|
|
{ "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
|
|
{ "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
|
|
{ "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
|
|
|
|
{ "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
|
|
{ "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
|
|
{ "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
|
|
|
|
/* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
|
|
{ "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
|
|
{ "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
|
|
{ "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
|
|
{ "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
|
|
{ "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
|
|
{ "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
|
|
{ "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
|
|
{ "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
|
|
{ "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
|
|
{ "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
|
|
{
|
|
"w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
|
|
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
|
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
|
|
},
|
|
{ "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
|
|
{ "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
|
|
{
|
|
"w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
|
|
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
|
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
|
|
},
|
|
{
|
|
"w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
|
|
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
|
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
|
|
},
|
|
{ "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
|
|
{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
|
|
{ "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
|
|
{ "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
|
|
|
|
/* Catalyst / On Semiconductor -- non-JEDEC */
|
|
{ "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
|
|
{ "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
|
|
{ "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
|
|
{ "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
|
|
{ "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
|
|
|
|
/* Xilinx S3AN Internal Flash */
|
|
{ "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
|
|
{ "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
|
|
{ "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
|
|
{ "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
|
|
{ "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
|
|
{ },
|
|
};
|
|
|
|
static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
|
|
{
|
|
int tmp;
|
|
u8 id[SPI_NOR_MAX_ID_LEN];
|
|
const struct flash_info *info;
|
|
|
|
tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
|
|
if (tmp < 0) {
|
|
dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
|
|
return ERR_PTR(tmp);
|
|
}
|
|
|
|
for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
|
|
info = &spi_nor_ids[tmp];
|
|
if (info->id_len) {
|
|
if (!memcmp(info->id, id, info->id_len))
|
|
return &spi_nor_ids[tmp];
|
|
}
|
|
}
|
|
dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
|
|
id[0], id[1], id[2]);
|
|
return ERR_PTR(-ENODEV);
|
|
}
|
|
|
|
static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
|
|
size_t *retlen, u_char *buf)
|
|
{
|
|
struct spi_nor *nor = mtd_to_spi_nor(mtd);
|
|
int ret;
|
|
|
|
dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
|
|
|
|
ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
|
|
if (ret)
|
|
return ret;
|
|
|
|
while (len) {
|
|
loff_t addr = from;
|
|
|
|
if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
|
|
addr = spi_nor_s3an_addr_convert(nor, addr);
|
|
|
|
ret = nor->read(nor, addr, len, buf);
|
|
if (ret == 0) {
|
|
/* We shouldn't see 0-length reads */
|
|
ret = -EIO;
|
|
goto read_err;
|
|
}
|
|
if (ret < 0)
|
|
goto read_err;
|
|
|
|
WARN_ON(ret > len);
|
|
*retlen += ret;
|
|
buf += ret;
|
|
from += ret;
|
|
len -= ret;
|
|
}
|
|
ret = 0;
|
|
|
|
read_err:
|
|
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
|
|
return ret;
|
|
}
|
|
|
|
static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
|
|
size_t *retlen, const u_char *buf)
|
|
{
|
|
struct spi_nor *nor = mtd_to_spi_nor(mtd);
|
|
size_t actual;
|
|
int ret;
|
|
|
|
dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
|
|
|
|
ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
|
|
if (ret)
|
|
return ret;
|
|
|
|
write_enable(nor);
|
|
|
|
nor->sst_write_second = false;
|
|
|
|
actual = to % 2;
|
|
/* Start write from odd address. */
|
|
if (actual) {
|
|
nor->program_opcode = SPINOR_OP_BP;
|
|
|
|
/* write one byte. */
|
|
ret = nor->write(nor, to, 1, buf);
|
|
if (ret < 0)
|
|
goto sst_write_err;
|
|
WARN(ret != 1, "While writing 1 byte written %i bytes\n",
|
|
(int)ret);
|
|
ret = spi_nor_wait_till_ready(nor);
|
|
if (ret)
|
|
goto sst_write_err;
|
|
}
|
|
to += actual;
|
|
|
|
/* Write out most of the data here. */
|
|
for (; actual < len - 1; actual += 2) {
|
|
nor->program_opcode = SPINOR_OP_AAI_WP;
|
|
|
|
/* write two bytes. */
|
|
ret = nor->write(nor, to, 2, buf + actual);
|
|
if (ret < 0)
|
|
goto sst_write_err;
|
|
WARN(ret != 2, "While writing 2 bytes written %i bytes\n",
|
|
(int)ret);
|
|
ret = spi_nor_wait_till_ready(nor);
|
|
if (ret)
|
|
goto sst_write_err;
|
|
to += 2;
|
|
nor->sst_write_second = true;
|
|
}
|
|
nor->sst_write_second = false;
|
|
|
|
write_disable(nor);
|
|
ret = spi_nor_wait_till_ready(nor);
|
|
if (ret)
|
|
goto sst_write_err;
|
|
|
|
/* Write out trailing byte if it exists. */
|
|
if (actual != len) {
|
|
write_enable(nor);
|
|
|
|
nor->program_opcode = SPINOR_OP_BP;
|
|
ret = nor->write(nor, to, 1, buf + actual);
|
|
if (ret < 0)
|
|
goto sst_write_err;
|
|
WARN(ret != 1, "While writing 1 byte written %i bytes\n",
|
|
(int)ret);
|
|
ret = spi_nor_wait_till_ready(nor);
|
|
if (ret)
|
|
goto sst_write_err;
|
|
write_disable(nor);
|
|
actual += 1;
|
|
}
|
|
sst_write_err:
|
|
*retlen += actual;
|
|
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Write an address range to the nor chip. Data must be written in
|
|
* FLASH_PAGESIZE chunks. The address range may be any size provided
|
|
* it is within the physical boundaries.
|
|
*/
|
|
static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
|
|
size_t *retlen, const u_char *buf)
|
|
{
|
|
struct spi_nor *nor = mtd_to_spi_nor(mtd);
|
|
size_t page_offset, page_remain, i;
|
|
ssize_t ret;
|
|
|
|
dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
|
|
|
|
ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
|
|
if (ret)
|
|
return ret;
|
|
|
|
for (i = 0; i < len; ) {
|
|
ssize_t written;
|
|
loff_t addr = to + i;
|
|
|
|
/*
|
|
* If page_size is a power of two, the offset can be quickly
|
|
* calculated with an AND operation. On the other cases we
|
|
* need to do a modulus operation (more expensive).
|
|
* Power of two numbers have only one bit set and we can use
|
|
* the instruction hweight32 to detect if we need to do a
|
|
* modulus (do_div()) or not.
|
|
*/
|
|
if (hweight32(nor->page_size) == 1) {
|
|
page_offset = addr & (nor->page_size - 1);
|
|
} else {
|
|
uint64_t aux = addr;
|
|
|
|
page_offset = do_div(aux, nor->page_size);
|
|
}
|
|
/* the size of data remaining on the first page */
|
|
page_remain = min_t(size_t,
|
|
nor->page_size - page_offset, len - i);
|
|
|
|
if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
|
|
addr = spi_nor_s3an_addr_convert(nor, addr);
|
|
|
|
write_enable(nor);
|
|
ret = nor->write(nor, addr, page_remain, buf + i);
|
|
if (ret < 0)
|
|
goto write_err;
|
|
written = ret;
|
|
|
|
ret = spi_nor_wait_till_ready(nor);
|
|
if (ret)
|
|
goto write_err;
|
|
*retlen += written;
|
|
i += written;
|
|
if (written != page_remain) {
|
|
dev_err(nor->dev,
|
|
"While writing %zu bytes written %zd bytes\n",
|
|
page_remain, written);
|
|
ret = -EIO;
|
|
goto write_err;
|
|
}
|
|
}
|
|
|
|
write_err:
|
|
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
|
|
return ret;
|
|
}
|
|
|
|
static int macronix_quad_enable(struct spi_nor *nor)
|
|
{
|
|
int ret, val;
|
|
|
|
val = read_sr(nor);
|
|
if (val < 0)
|
|
return val;
|
|
if (val & SR_QUAD_EN_MX)
|
|
return 0;
|
|
|
|
write_enable(nor);
|
|
|
|
write_sr(nor, val | SR_QUAD_EN_MX);
|
|
|
|
if (spi_nor_wait_till_ready(nor))
|
|
return 1;
|
|
|
|
ret = read_sr(nor);
|
|
if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
|
|
dev_err(nor->dev, "Macronix Quad bit not set\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Write status Register and configuration register with 2 bytes
|
|
* The first byte will be written to the status register, while the
|
|
* second byte will be written to the configuration register.
|
|
* Return negative if error occurred.
|
|
*/
|
|
static int write_sr_cr(struct spi_nor *nor, u16 val)
|
|
{
|
|
nor->cmd_buf[0] = val & 0xff;
|
|
nor->cmd_buf[1] = (val >> 8);
|
|
|
|
return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
|
|
}
|
|
|
|
static int spansion_quad_enable(struct spi_nor *nor)
|
|
{
|
|
int ret;
|
|
int quad_en = CR_QUAD_EN_SPAN << 8;
|
|
|
|
write_enable(nor);
|
|
|
|
ret = write_sr_cr(nor, quad_en);
|
|
if (ret < 0) {
|
|
dev_err(nor->dev,
|
|
"error while writing configuration register\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = spi_nor_wait_till_ready(nor);
|
|
if (ret) {
|
|
dev_err(nor->dev,
|
|
"timeout while writing configuration register\n");
|
|
return ret;
|
|
}
|
|
|
|
/* read back and check it */
|
|
ret = read_cr(nor);
|
|
if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
|
|
dev_err(nor->dev, "Spansion Quad bit not set\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int spi_nor_check(struct spi_nor *nor)
|
|
{
|
|
if (!nor->dev || !nor->read || !nor->write ||
|
|
!nor->read_reg || !nor->write_reg) {
|
|
pr_err("spi-nor: please fill all the necessary fields!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor)
|
|
{
|
|
int ret;
|
|
u8 val;
|
|
|
|
ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
|
|
if (ret < 0) {
|
|
dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
|
|
return ret;
|
|
}
|
|
|
|
nor->erase_opcode = SPINOR_OP_XSE;
|
|
nor->program_opcode = SPINOR_OP_XPP;
|
|
nor->read_opcode = SPINOR_OP_READ;
|
|
nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
|
|
|
|
/*
|
|
* This flashes have a page size of 264 or 528 bytes (known as
|
|
* Default addressing mode). It can be changed to a more standard
|
|
* Power of two mode where the page size is 256/512. This comes
|
|
* with a price: there is 3% less of space, the data is corrupted
|
|
* and the page size cannot be changed back to default addressing
|
|
* mode.
|
|
*
|
|
* The current addressing mode can be read from the XRDSR register
|
|
* and should not be changed, because is a destructive operation.
|
|
*/
|
|
if (val & XSR_PAGESIZE) {
|
|
/* Flash in Power of 2 mode */
|
|
nor->page_size = (nor->page_size == 264) ? 256 : 512;
|
|
nor->mtd.writebufsize = nor->page_size;
|
|
nor->mtd.size = 8 * nor->page_size * info->n_sectors;
|
|
nor->mtd.erasesize = 8 * nor->page_size;
|
|
} else {
|
|
/* Flash in Default addressing mode */
|
|
nor->flags |= SNOR_F_S3AN_ADDR_DEFAULT;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct spi_nor_read_command {
|
|
u8 num_mode_clocks;
|
|
u8 num_wait_states;
|
|
u8 opcode;
|
|
enum spi_nor_protocol proto;
|
|
};
|
|
|
|
struct spi_nor_pp_command {
|
|
u8 opcode;
|
|
enum spi_nor_protocol proto;
|
|
};
|
|
|
|
enum spi_nor_read_command_index {
|
|
SNOR_CMD_READ,
|
|
SNOR_CMD_READ_FAST,
|
|
|
|
/* Dual SPI */
|
|
SNOR_CMD_READ_1_1_2,
|
|
SNOR_CMD_READ_1_2_2,
|
|
SNOR_CMD_READ_2_2_2,
|
|
|
|
/* Quad SPI */
|
|
SNOR_CMD_READ_1_1_4,
|
|
SNOR_CMD_READ_1_4_4,
|
|
SNOR_CMD_READ_4_4_4,
|
|
|
|
SNOR_CMD_READ_MAX
|
|
};
|
|
|
|
enum spi_nor_pp_command_index {
|
|
SNOR_CMD_PP,
|
|
|
|
/* Quad SPI */
|
|
SNOR_CMD_PP_1_1_4,
|
|
SNOR_CMD_PP_1_4_4,
|
|
SNOR_CMD_PP_4_4_4,
|
|
|
|
SNOR_CMD_PP_MAX
|
|
};
|
|
|
|
struct spi_nor_flash_parameter {
|
|
u64 size;
|
|
u32 page_size;
|
|
|
|
struct spi_nor_hwcaps hwcaps;
|
|
struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
|
|
struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
|
|
|
|
int (*quad_enable)(struct spi_nor *nor);
|
|
};
|
|
|
|
static void
|
|
spi_nor_set_read_settings(struct spi_nor_read_command *read,
|
|
u8 num_mode_clocks,
|
|
u8 num_wait_states,
|
|
u8 opcode,
|
|
enum spi_nor_protocol proto)
|
|
{
|
|
read->num_mode_clocks = num_mode_clocks;
|
|
read->num_wait_states = num_wait_states;
|
|
read->opcode = opcode;
|
|
read->proto = proto;
|
|
}
|
|
|
|
static void
|
|
spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
|
|
u8 opcode,
|
|
enum spi_nor_protocol proto)
|
|
{
|
|
pp->opcode = opcode;
|
|
pp->proto = proto;
|
|
}
|
|
|
|
static int spi_nor_init_params(struct spi_nor *nor,
|
|
const struct flash_info *info,
|
|
struct spi_nor_flash_parameter *params)
|
|
{
|
|
/* Set legacy flash parameters as default. */
|
|
memset(params, 0, sizeof(*params));
|
|
|
|
/* Set SPI NOR sizes. */
|
|
params->size = info->sector_size * info->n_sectors;
|
|
params->page_size = info->page_size;
|
|
|
|
/* (Fast) Read settings. */
|
|
params->hwcaps.mask |= SNOR_HWCAPS_READ;
|
|
spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
|
|
0, 0, SPINOR_OP_READ,
|
|
SNOR_PROTO_1_1_1);
|
|
|
|
if (!(info->flags & SPI_NOR_NO_FR)) {
|
|
params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
|
|
spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
|
|
0, 8, SPINOR_OP_READ_FAST,
|
|
SNOR_PROTO_1_1_1);
|
|
}
|
|
|
|
if (info->flags & SPI_NOR_DUAL_READ) {
|
|
params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
|
|
spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
|
|
0, 8, SPINOR_OP_READ_1_1_2,
|
|
SNOR_PROTO_1_1_2);
|
|
}
|
|
|
|
if (info->flags & SPI_NOR_QUAD_READ) {
|
|
params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
|
|
spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
|
|
0, 8, SPINOR_OP_READ_1_1_4,
|
|
SNOR_PROTO_1_1_4);
|
|
}
|
|
|
|
/* Page Program settings. */
|
|
params->hwcaps.mask |= SNOR_HWCAPS_PP;
|
|
spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
|
|
SPINOR_OP_PP, SNOR_PROTO_1_1_1);
|
|
|
|
/* Select the procedure to set the Quad Enable bit. */
|
|
if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
|
|
SNOR_HWCAPS_PP_QUAD)) {
|
|
switch (JEDEC_MFR(info)) {
|
|
case SNOR_MFR_MACRONIX:
|
|
params->quad_enable = macronix_quad_enable;
|
|
break;
|
|
|
|
case SNOR_MFR_MICRON:
|
|
break;
|
|
|
|
default:
|
|
params->quad_enable = spansion_quad_enable;
|
|
break;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
|
|
{
|
|
size_t i;
|
|
|
|
for (i = 0; i < size; i++)
|
|
if (table[i][0] == (int)hwcaps)
|
|
return table[i][1];
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
|
|
{
|
|
static const int hwcaps_read2cmd[][2] = {
|
|
{ SNOR_HWCAPS_READ, SNOR_CMD_READ },
|
|
{ SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
|
|
{ SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
|
|
{ SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
|
|
{ SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
|
|
{ SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
|
|
{ SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
|
|
{ SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
|
|
};
|
|
|
|
return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
|
|
ARRAY_SIZE(hwcaps_read2cmd));
|
|
}
|
|
|
|
static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
|
|
{
|
|
static const int hwcaps_pp2cmd[][2] = {
|
|
{ SNOR_HWCAPS_PP, SNOR_CMD_PP },
|
|
{ SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
|
|
{ SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
|
|
{ SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
|
|
};
|
|
|
|
return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
|
|
ARRAY_SIZE(hwcaps_pp2cmd));
|
|
}
|
|
|
|
static int spi_nor_select_read(struct spi_nor *nor,
|
|
const struct spi_nor_flash_parameter *params,
|
|
u32 shared_hwcaps)
|
|
{
|
|
int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
|
|
const struct spi_nor_read_command *read;
|
|
|
|
if (best_match < 0)
|
|
return -EINVAL;
|
|
|
|
cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
|
|
if (cmd < 0)
|
|
return -EINVAL;
|
|
|
|
read = ¶ms->reads[cmd];
|
|
nor->read_opcode = read->opcode;
|
|
nor->read_proto = read->proto;
|
|
|
|
/*
|
|
* In the spi-nor framework, we don't need to make the difference
|
|
* between mode clock cycles and wait state clock cycles.
|
|
* Indeed, the value of the mode clock cycles is used by a QSPI
|
|
* flash memory to know whether it should enter or leave its 0-4-4
|
|
* (Continuous Read / XIP) mode.
|
|
* eXecution In Place is out of the scope of the mtd sub-system.
|
|
* Hence we choose to merge both mode and wait state clock cycles
|
|
* into the so called dummy clock cycles.
|
|
*/
|
|
nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
|
|
return 0;
|
|
}
|
|
|
|
static int spi_nor_select_pp(struct spi_nor *nor,
|
|
const struct spi_nor_flash_parameter *params,
|
|
u32 shared_hwcaps)
|
|
{
|
|
int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
|
|
const struct spi_nor_pp_command *pp;
|
|
|
|
if (best_match < 0)
|
|
return -EINVAL;
|
|
|
|
cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
|
|
if (cmd < 0)
|
|
return -EINVAL;
|
|
|
|
pp = ¶ms->page_programs[cmd];
|
|
nor->program_opcode = pp->opcode;
|
|
nor->write_proto = pp->proto;
|
|
return 0;
|
|
}
|
|
|
|
static int spi_nor_select_erase(struct spi_nor *nor,
|
|
const struct flash_info *info)
|
|
{
|
|
struct mtd_info *mtd = &nor->mtd;
|
|
|
|
#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
|
|
/* prefer "small sector" erase if possible */
|
|
if (info->flags & SECT_4K) {
|
|
nor->erase_opcode = SPINOR_OP_BE_4K;
|
|
mtd->erasesize = 4096;
|
|
} else if (info->flags & SECT_4K_PMC) {
|
|
nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
|
|
mtd->erasesize = 4096;
|
|
} else
|
|
#endif
|
|
{
|
|
nor->erase_opcode = SPINOR_OP_SE;
|
|
mtd->erasesize = info->sector_size;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
|
|
const struct spi_nor_flash_parameter *params,
|
|
const struct spi_nor_hwcaps *hwcaps)
|
|
{
|
|
u32 ignored_mask, shared_mask;
|
|
bool enable_quad_io;
|
|
int err;
|
|
|
|
/*
|
|
* Keep only the hardware capabilities supported by both the SPI
|
|
* controller and the SPI flash memory.
|
|
*/
|
|
shared_mask = hwcaps->mask & params->hwcaps.mask;
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|
|
|
/* SPI n-n-n protocols are not supported yet. */
|
|
ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
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SNOR_HWCAPS_READ_4_4_4 |
|
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SNOR_HWCAPS_PP_4_4_4);
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if (shared_mask & ignored_mask) {
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dev_dbg(nor->dev,
|
|
"SPI n-n-n protocols are not supported yet.\n");
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|
shared_mask &= ~ignored_mask;
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|
}
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|
|
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/* Select the (Fast) Read command. */
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err = spi_nor_select_read(nor, params, shared_mask);
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if (err) {
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dev_err(nor->dev,
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"can't select read settings supported by both the SPI controller and memory.\n");
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|
return err;
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|
}
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|
|
|
/* Select the Page Program command. */
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|
err = spi_nor_select_pp(nor, params, shared_mask);
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if (err) {
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|
dev_err(nor->dev,
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|
"can't select write settings supported by both the SPI controller and memory.\n");
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|
return err;
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|
}
|
|
|
|
/* Select the Sector Erase command. */
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|
err = spi_nor_select_erase(nor, info);
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if (err) {
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dev_err(nor->dev,
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|
"can't select erase settings supported by both the SPI controller and memory.\n");
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|
return err;
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|
}
|
|
|
|
/* Enable Quad I/O if needed. */
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enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
|
|
spi_nor_get_protocol_width(nor->write_proto) == 4);
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if (enable_quad_io && params->quad_enable) {
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err = params->quad_enable(nor);
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|
if (err) {
|
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dev_err(nor->dev, "quad mode not supported\n");
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|
return err;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int spi_nor_scan(struct spi_nor *nor, const char *name,
|
|
const struct spi_nor_hwcaps *hwcaps)
|
|
{
|
|
struct spi_nor_flash_parameter params;
|
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const struct flash_info *info = NULL;
|
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struct device *dev = nor->dev;
|
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struct mtd_info *mtd = &nor->mtd;
|
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struct device_node *np = spi_nor_get_flash_node(nor);
|
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int ret;
|
|
int i;
|
|
|
|
ret = spi_nor_check(nor);
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if (ret)
|
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return ret;
|
|
|
|
/* Reset SPI protocol for all commands. */
|
|
nor->reg_proto = SNOR_PROTO_1_1_1;
|
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nor->read_proto = SNOR_PROTO_1_1_1;
|
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nor->write_proto = SNOR_PROTO_1_1_1;
|
|
|
|
if (name)
|
|
info = spi_nor_match_id(name);
|
|
/* Try to auto-detect if chip name wasn't specified or not found */
|
|
if (!info)
|
|
info = spi_nor_read_id(nor);
|
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if (IS_ERR_OR_NULL(info))
|
|
return -ENOENT;
|
|
|
|
/*
|
|
* If caller has specified name of flash model that can normally be
|
|
* detected using JEDEC, let's verify it.
|
|
*/
|
|
if (name && info->id_len) {
|
|
const struct flash_info *jinfo;
|
|
|
|
jinfo = spi_nor_read_id(nor);
|
|
if (IS_ERR(jinfo)) {
|
|
return PTR_ERR(jinfo);
|
|
} else if (jinfo != info) {
|
|
/*
|
|
* JEDEC knows better, so overwrite platform ID. We
|
|
* can't trust partitions any longer, but we'll let
|
|
* mtd apply them anyway, since some partitions may be
|
|
* marked read-only, and we don't want to lose that
|
|
* information, even if it's not 100% accurate.
|
|
*/
|
|
dev_warn(dev, "found %s, expected %s\n",
|
|
jinfo->name, info->name);
|
|
info = jinfo;
|
|
}
|
|
}
|
|
|
|
mutex_init(&nor->lock);
|
|
|
|
/*
|
|
* Make sure the XSR_RDY flag is set before calling
|
|
* spi_nor_wait_till_ready(). Xilinx S3AN share MFR
|
|
* with Atmel spi-nor
|
|
*/
|
|
if (info->flags & SPI_S3AN)
|
|
nor->flags |= SNOR_F_READY_XSR_RDY;
|
|
|
|
/* Parse the Serial Flash Discoverable Parameters table. */
|
|
ret = spi_nor_init_params(nor, info, ¶ms);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
|
|
* with the software protection bits set
|
|
*/
|
|
|
|
if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
|
|
JEDEC_MFR(info) == SNOR_MFR_INTEL ||
|
|
JEDEC_MFR(info) == SNOR_MFR_SST ||
|
|
info->flags & SPI_NOR_HAS_LOCK) {
|
|
write_enable(nor);
|
|
write_sr(nor, 0);
|
|
spi_nor_wait_till_ready(nor);
|
|
}
|
|
|
|
if (!mtd->name)
|
|
mtd->name = dev_name(dev);
|
|
mtd->priv = nor;
|
|
mtd->type = MTD_NORFLASH;
|
|
mtd->writesize = 1;
|
|
mtd->flags = MTD_CAP_NORFLASH;
|
|
mtd->size = params.size;
|
|
mtd->_erase = spi_nor_erase;
|
|
mtd->_read = spi_nor_read;
|
|
|
|
/* NOR protection support for STmicro/Micron chips and similar */
|
|
if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
|
|
info->flags & SPI_NOR_HAS_LOCK) {
|
|
nor->flash_lock = stm_lock;
|
|
nor->flash_unlock = stm_unlock;
|
|
nor->flash_is_locked = stm_is_locked;
|
|
}
|
|
|
|
if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
|
|
mtd->_lock = spi_nor_lock;
|
|
mtd->_unlock = spi_nor_unlock;
|
|
mtd->_is_locked = spi_nor_is_locked;
|
|
}
|
|
|
|
/* sst nor chips use AAI word program */
|
|
if (info->flags & SST_WRITE)
|
|
mtd->_write = sst_write;
|
|
else
|
|
mtd->_write = spi_nor_write;
|
|
|
|
if (info->flags & USE_FSR)
|
|
nor->flags |= SNOR_F_USE_FSR;
|
|
if (info->flags & SPI_NOR_HAS_TB)
|
|
nor->flags |= SNOR_F_HAS_SR_TB;
|
|
if (info->flags & NO_CHIP_ERASE)
|
|
nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
|
|
|
|
if (info->flags & SPI_NOR_NO_ERASE)
|
|
mtd->flags |= MTD_NO_ERASE;
|
|
|
|
mtd->dev.parent = dev;
|
|
nor->page_size = params.page_size;
|
|
mtd->writebufsize = nor->page_size;
|
|
|
|
if (np) {
|
|
/* If we were instantiated by DT, use it */
|
|
if (of_property_read_bool(np, "m25p,fast-read"))
|
|
params.hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
|
|
else
|
|
params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
|
|
} else {
|
|
/* If we weren't instantiated by DT, default to fast-read */
|
|
params.hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
|
|
}
|
|
|
|
/* Some devices cannot do fast-read, no matter what DT tells us */
|
|
if (info->flags & SPI_NOR_NO_FR)
|
|
params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
|
|
|
|
/*
|
|
* Configure the SPI memory:
|
|
* - select op codes for (Fast) Read, Page Program and Sector Erase.
|
|
* - set the number of dummy cycles (mode cycles + wait states).
|
|
* - set the SPI protocols for register and memory accesses.
|
|
* - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
|
|
*/
|
|
ret = spi_nor_setup(nor, info, ¶ms, hwcaps);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (info->addr_width)
|
|
nor->addr_width = info->addr_width;
|
|
else if (mtd->size > 0x1000000) {
|
|
/* enable 4-byte addressing if the device exceeds 16MiB */
|
|
nor->addr_width = 4;
|
|
if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
|
|
info->flags & SPI_NOR_4B_OPCODES)
|
|
spi_nor_set_4byte_opcodes(nor, info);
|
|
else
|
|
set_4byte(nor, info, 1);
|
|
} else {
|
|
nor->addr_width = 3;
|
|
}
|
|
|
|
if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
|
|
dev_err(dev, "address width is too large: %u\n",
|
|
nor->addr_width);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (info->flags & SPI_S3AN) {
|
|
ret = s3an_nor_scan(info, nor);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
dev_info(dev, "%s (%lld Kbytes)\n", info->name,
|
|
(long long)mtd->size >> 10);
|
|
|
|
dev_dbg(dev,
|
|
"mtd .name = %s, .size = 0x%llx (%lldMiB), "
|
|
".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
|
|
mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
|
|
mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
|
|
|
|
if (mtd->numeraseregions)
|
|
for (i = 0; i < mtd->numeraseregions; i++)
|
|
dev_dbg(dev,
|
|
"mtd.eraseregions[%d] = { .offset = 0x%llx, "
|
|
".erasesize = 0x%.8x (%uKiB), "
|
|
".numblocks = %d }\n",
|
|
i, (long long)mtd->eraseregions[i].offset,
|
|
mtd->eraseregions[i].erasesize,
|
|
mtd->eraseregions[i].erasesize / 1024,
|
|
mtd->eraseregions[i].numblocks);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(spi_nor_scan);
|
|
|
|
static const struct flash_info *spi_nor_match_id(const char *name)
|
|
{
|
|
const struct flash_info *id = spi_nor_ids;
|
|
|
|
while (id->name) {
|
|
if (!strcmp(name, id->name))
|
|
return id;
|
|
id++;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
|
|
MODULE_AUTHOR("Mike Lavender");
|
|
MODULE_DESCRIPTION("framework for SPI NOR");
|