forked from Minki/linux
753a71090f
One of main changes of GMAC 4.xx IP is descriptors management.
-descriptors are only used in ring mode.
-A descriptor is composed of 4 32bits registers (no more extended
descriptors)
-descriptor mechanism (Tx for example, but it is exactly the same for RX):
-useful registers:
-DMA_CH#_TxDesc_Ring_Len: length of transmit descriptor
ring
-DMA_CH#_TxDesc_List_Address: start address of the ring
-DMA_CH#_TxDesc_Tail_Pointer: address of the last
descriptor to send + 1.
-DMA_CH#_TxDesc_Current_App_TxDesc: address of the current
descriptor
-The descriptor Tail Pointer register contains the pointer to the
descriptor address (N). The base address and the current
descriptor decide the address of the current descriptor that the
DMA can process. The descriptors up to one location less than the
one indicated by the descriptor tail pointer (N-1) are owned by
the DMA. The DMA continues to process the descriptors until the
following condition occurs:
"current descriptor pointer == Descriptor Tail pointer"
Then the DMA goes into suspend mode. The application must perform
a write to descriptor tail pointer register and update the tail
pointer to have the following condition and to start a new
transfer:
"current descriptor pointer < Descriptor tail pointer"
The DMA automatically wraps around the base address when the end
of ring is reached.
-New features are available on IP:
-TSO (TCP Segmentation Offload) for TX only
-Split header: to have header and payload in 2 different buffers
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
130 lines
4.3 KiB
C
130 lines
4.3 KiB
C
/*
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* Header File to describe the DMA descriptors and related definitions specific
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* for DesignWare databook 4.xx.
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*
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* Copyright (C) 2015 STMicroelectronics Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* Author: Alexandre Torgue <alexandre.torgue@st.com>
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*/
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#ifndef __DWMAC4_DESCS_H__
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#define __DWMAC4_DESCS_H__
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#include <linux/bitops.h>
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/* Normal transmit descriptor defines (without split feature) */
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/* TDES2 (read format) */
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#define TDES2_BUFFER1_SIZE_MASK GENMASK(13, 0)
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#define TDES2_VLAN_TAG_MASK GENMASK(15, 14)
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#define TDES2_BUFFER2_SIZE_MASK GENMASK(29, 16)
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#define TDES2_BUFFER2_SIZE_MASK_SHIFT 16
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#define TDES2_TIMESTAMP_ENABLE BIT(30)
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#define TDES2_INTERRUPT_ON_COMPLETION BIT(31)
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/* TDES3 (read format) */
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#define TDES3_PACKET_SIZE_MASK GENMASK(14, 0)
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#define TDES3_CHECKSUM_INSERTION_MASK GENMASK(17, 16)
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#define TDES3_CHECKSUM_INSERTION_SHIFT 16
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#define TDES3_TCP_PKT_PAYLOAD_MASK GENMASK(17, 0)
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#define TDES3_TCP_SEGMENTATION_ENABLE BIT(18)
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#define TDES3_HDR_LEN_SHIFT 19
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#define TDES3_SLOT_NUMBER_MASK GENMASK(22, 19)
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#define TDES3_SA_INSERT_CTRL_MASK GENMASK(25, 23)
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#define TDES3_CRC_PAD_CTRL_MASK GENMASK(27, 26)
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/* TDES3 (write back format) */
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#define TDES3_IP_HDR_ERROR BIT(0)
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#define TDES3_DEFERRED BIT(1)
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#define TDES3_UNDERFLOW_ERROR BIT(2)
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#define TDES3_EXCESSIVE_DEFERRAL BIT(3)
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#define TDES3_COLLISION_COUNT_MASK GENMASK(7, 4)
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#define TDES3_COLLISION_COUNT_SHIFT 4
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#define TDES3_EXCESSIVE_COLLISION BIT(8)
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#define TDES3_LATE_COLLISION BIT(9)
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#define TDES3_NO_CARRIER BIT(10)
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#define TDES3_LOSS_CARRIER BIT(11)
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#define TDES3_PAYLOAD_ERROR BIT(12)
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#define TDES3_PACKET_FLUSHED BIT(13)
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#define TDES3_JABBER_TIMEOUT BIT(14)
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#define TDES3_ERROR_SUMMARY BIT(15)
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#define TDES3_TIMESTAMP_STATUS BIT(17)
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#define TDES3_TIMESTAMP_STATUS_SHIFT 17
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/* TDES3 context */
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#define TDES3_CTXT_TCMSSV BIT(26)
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/* TDES3 Common */
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#define TDES3_LAST_DESCRIPTOR BIT(28)
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#define TDES3_LAST_DESCRIPTOR_SHIFT 28
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#define TDES3_FIRST_DESCRIPTOR BIT(29)
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#define TDES3_CONTEXT_TYPE BIT(30)
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/* TDS3 use for both format (read and write back) */
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#define TDES3_OWN BIT(31)
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#define TDES3_OWN_SHIFT 31
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/* Normal receive descriptor defines (without split feature) */
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/* RDES0 (write back format) */
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#define RDES0_VLAN_TAG_MASK GENMASK(15, 0)
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/* RDES1 (write back format) */
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#define RDES1_IP_PAYLOAD_TYPE_MASK GENMASK(2, 0)
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#define RDES1_IP_HDR_ERROR BIT(3)
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#define RDES1_IPV4_HEADER BIT(4)
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#define RDES1_IPV6_HEADER BIT(5)
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#define RDES1_IP_CSUM_BYPASSED BIT(6)
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#define RDES1_IP_CSUM_ERROR BIT(7)
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#define RDES1_PTP_MSG_TYPE_MASK GENMASK(11, 8)
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#define RDES1_PTP_PACKET_TYPE BIT(12)
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#define RDES1_PTP_VER BIT(13)
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#define RDES1_TIMESTAMP_AVAILABLE BIT(14)
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#define RDES1_TIMESTAMP_AVAILABLE_SHIFT 14
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#define RDES1_TIMESTAMP_DROPPED BIT(15)
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#define RDES1_IP_TYPE1_CSUM_MASK GENMASK(31, 16)
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/* RDES2 (write back format) */
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#define RDES2_L3_L4_HEADER_SIZE_MASK GENMASK(9, 0)
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#define RDES2_VLAN_FILTER_STATUS BIT(15)
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#define RDES2_SA_FILTER_FAIL BIT(16)
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#define RDES2_DA_FILTER_FAIL BIT(17)
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#define RDES2_HASH_FILTER_STATUS BIT(18)
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#define RDES2_MAC_ADDR_MATCH_MASK GENMASK(26, 19)
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#define RDES2_HASH_VALUE_MATCH_MASK GENMASK(26, 19)
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#define RDES2_L3_FILTER_MATCH BIT(27)
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#define RDES2_L4_FILTER_MATCH BIT(28)
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#define RDES2_L3_L4_FILT_NB_MATCH_MASK GENMASK(27, 26)
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#define RDES2_L3_L4_FILT_NB_MATCH_SHIFT 26
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/* RDES3 (write back format) */
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#define RDES3_PACKET_SIZE_MASK GENMASK(14, 0)
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#define RDES3_ERROR_SUMMARY BIT(15)
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#define RDES3_PACKET_LEN_TYPE_MASK GENMASK(18, 16)
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#define RDES3_DRIBBLE_ERROR BIT(19)
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#define RDES3_RECEIVE_ERROR BIT(20)
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#define RDES3_OVERFLOW_ERROR BIT(21)
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#define RDES3_RECEIVE_WATCHDOG BIT(22)
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#define RDES3_GIANT_PACKET BIT(23)
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#define RDES3_CRC_ERROR BIT(24)
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#define RDES3_RDES0_VALID BIT(25)
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#define RDES3_RDES1_VALID BIT(26)
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#define RDES3_RDES2_VALID BIT(27)
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#define RDES3_LAST_DESCRIPTOR BIT(28)
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#define RDES3_FIRST_DESCRIPTOR BIT(29)
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#define RDES3_CONTEXT_DESCRIPTOR BIT(30)
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/* RDES3 (read format) */
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#define RDES3_BUFFER1_VALID_ADDR BIT(24)
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#define RDES3_BUFFER2_VALID_ADDR BIT(25)
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#define RDES3_INT_ON_COMPLETION_EN BIT(30)
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/* TDS3 use for both format (read and write back) */
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#define RDES3_OWN BIT(31)
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#endif /* __DWMAC4_DESCS_H__ */
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