forked from Minki/linux
6eb5d146d4
Before it isn't too late let's switch to IO memory accessors. This patch converts all current _REG users and _REG definitions. There should be no functional changes. Suggested-by: Ben Dooks <ben-linux@fluff.org> Suggested-by: Sergei Shtylyov <sshtylyov@mvista.com> Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
102 lines
2.2 KiB
C
102 lines
2.2 KiB
C
/*
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* Copyright 2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <mach/system.h>
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#include <mach/cns3xxx.h>
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void cns3xxx_pwr_clk_en(unsigned int block)
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{
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u32 reg = __raw_readl(PM_CLK_GATE_REG);
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reg |= (block & PM_CLK_GATE_REG_MASK);
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__raw_writel(reg, PM_CLK_GATE_REG);
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}
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void cns3xxx_pwr_power_up(unsigned int block)
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{
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u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
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reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
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__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
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/* Wait for 300us for the PLL output clock locked. */
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udelay(300);
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};
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void cns3xxx_pwr_power_down(unsigned int block)
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{
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u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
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/* write '1' to power down */
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reg |= (block & CNS3XXX_PWR_PLL_ALL);
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__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
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};
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static void cns3xxx_pwr_soft_rst_force(unsigned int block)
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{
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u32 reg = __raw_readl(PM_SOFT_RST_REG);
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/*
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* bit 0, 28, 29 => program low to reset,
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* the other else program low and then high
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*/
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if (block & 0x30000001) {
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reg &= ~(block & PM_SOFT_RST_REG_MASK);
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} else {
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reg &= ~(block & PM_SOFT_RST_REG_MASK);
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reg |= (block & PM_SOFT_RST_REG_MASK);
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}
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__raw_writel(reg, PM_SOFT_RST_REG);
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}
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void cns3xxx_pwr_soft_rst(unsigned int block)
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{
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static unsigned int soft_reset;
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if (soft_reset & block) {
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/* SPI/I2C/GPIO use the same block, reset once. */
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return;
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} else {
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soft_reset |= block;
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}
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cns3xxx_pwr_soft_rst_force(block);
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}
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void arch_reset(char mode, const char *cmd)
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{
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/*
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* To reset, we hit the on-board reset register
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* in the system FPGA.
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*/
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cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
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}
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/*
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* cns3xxx_cpu_clock - return CPU/L2 clock
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* aclk: cpu clock/2
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* hclk: cpu clock/4
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* pclk: cpu clock/8
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*/
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int cns3xxx_cpu_clock(void)
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{
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u32 reg = __raw_readl(PM_CLK_CTRL_REG);
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int cpu;
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int cpu_sel;
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int div_sel;
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cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
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div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
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cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
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return cpu;
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}
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