forked from Minki/linux
bca10b906f
Handling System MMUs with an identifier is not flexible to manage System MMU platform devices because of the following reasons: 1. A device driver which needs to handle System MMU must know the ID. 2. A System MMU may not present in some implementations of Exynos family. 3. Handling System MMU with IOMMU API does not require an ID. This patch is the result of removing ID of System MMUs. Instead, a device driver that needs to handle its System MMU must use IOMMU API while its descriptor of platform device is given. This patch also includes the following enhancements: - A System MMU device becomes a child if its power domain device. - clkdev Signed-off-by: KyongHo Cho <pullip.cho@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
146 lines
3.5 KiB
C
146 lines
3.5 KiB
C
/*
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* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4212 - Clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/syscore_ops.h>
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#include <plat/cpu-freq.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/pll.h>
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#include <plat/s5p-clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/pm.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/sysmmu.h>
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#include "common.h"
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#include "clock-exynos4.h"
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#ifdef CONFIG_PM_SLEEP
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static struct sleep_save exynos4212_clock_save[] = {
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SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
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SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
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SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
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SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
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};
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#endif
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static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
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}
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static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
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}
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static struct clk *clk_src_mpll_user_list[] = {
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[0] = &clk_fin_mpll,
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[1] = &exynos4_clk_mout_mpll.clk,
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};
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static struct clksrc_sources clk_src_mpll_user = {
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.sources = clk_src_mpll_user_list,
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.nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
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};
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static struct clksrc_clk clk_mout_mpll_user = {
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.clk = {
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.name = "mout_mpll_user",
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},
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.sources = &clk_src_mpll_user,
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.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
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};
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static struct clksrc_clk *sysclks[] = {
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&clk_mout_mpll_user,
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};
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static struct clksrc_clk clksrcs[] = {
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/* nothing here yet */
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};
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static struct clk init_clocks_off[] = {
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{
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
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.enable = exynos4_clk_ip_dmc_ctrl,
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.ctrlbit = (1 << 24),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
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.enable = exynos4212_clk_ip_isp0_ctrl,
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.ctrlbit = (7 << 8),
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}, {
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.name = SYSMMU_CLOCK_NAME2,
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.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
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.enable = exynos4212_clk_ip_isp1_ctrl,
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.ctrlbit = (1 << 4),
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}
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};
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#ifdef CONFIG_PM_SLEEP
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static int exynos4212_clock_suspend(void)
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{
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s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
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return 0;
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}
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static void exynos4212_clock_resume(void)
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{
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s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
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}
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#else
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#define exynos4212_clock_suspend NULL
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#define exynos4212_clock_resume NULL
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#endif
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static struct syscore_ops exynos4212_clock_syscore_ops = {
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.suspend = exynos4212_clock_suspend,
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.resume = exynos4212_clock_resume,
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};
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void __init exynos4212_register_clocks(void)
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{
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int ptr;
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/* usbphy1 is removed */
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exynos4_clkset_group_list[4] = NULL;
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/* mout_mpll_user is used */
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exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
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exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
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exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
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exynos4_clk_mout_mpll.reg_src.shift = 12;
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exynos4_clk_mout_mpll.reg_src.size = 1;
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for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
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s3c_register_clksrc(sysclks[ptr], 1);
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s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
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s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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register_syscore_ops(&exynos4212_clock_syscore_ops);
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}
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