forked from Minki/linux
b120612206
GPMI driver timings derivation looks very empirical and does not use the known timings that the core wants to use with the NAND chip, by using local defined constants that have no special meaning from the outside world. Simplify the way all of this is computed and use the NAND core's SDR timings. Integrity of the reads/writes has been checked with nandbiterrs, speed improvements with flash_speed on a Freescale i.MX6 DualLite/Solo SABRE Automotive Board. Measures are below, variations of less than 150kiB/s between tests are common and then not significant. Speeds using mode 5 are the same, while speeds using mode 0 are quite improved (+40/50% from non-optimal computation). Forcing timings mode 0: ======================= Before this patch: ------------------ eraseblock write speed is 2298 KiB/s eraseblock read speed is 3636 KiB/s page write speed is 2136 KiB/s page read speed is 3316 KiB/s 2 page write speed is 2199 KiB/s 2 page read speed is 3468 KiB/s After this patch: ----------------- eraseblock write speed is 3232 KiB/s eraseblock read speed is 5663 KiB/s page write speed is 2915 KiB/s page read speed is 4904 KiB/s 2 page write speed is 3084 KiB/s 2 page read speed is 5267 KiB/s Forcing timings mode 5: ======================= Before this patch: ------------------ eraseblock write speed is 4338 KiB/s eraseblock read speed is 14883 KiB/s page write speed is 3786 KiB/s page read speed is 12800 KiB/s 2 page write speed is 4076 KiB/s 2 page read speed is 14065 KiB/s After this patch: ----------------- eraseblock write speed is 4309 KiB/s eraseblock read speed is 14712 KiB/s page write speed is 3764 KiB/s page read speed is 12673 KiB/s 2 page write speed is 4076 KiB/s 2 page read speed is 14065 KiB/s Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
193 lines
7.3 KiB
C
193 lines
7.3 KiB
C
/*
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* Freescale GPMI NAND Flash Driver
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*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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* Copyright 2008 Embedded Alley Solutions, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef __GPMI_NAND_GPMI_REGS_H
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#define __GPMI_NAND_GPMI_REGS_H
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#define HW_GPMI_CTRL0 0x00000000
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#define HW_GPMI_CTRL0_SET 0x00000004
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#define HW_GPMI_CTRL0_CLR 0x00000008
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#define HW_GPMI_CTRL0_TOG 0x0000000c
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#define BP_GPMI_CTRL0_COMMAND_MODE 24
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#define BM_GPMI_CTRL0_COMMAND_MODE (3 << BP_GPMI_CTRL0_COMMAND_MODE)
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#define BF_GPMI_CTRL0_COMMAND_MODE(v) \
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(((v) << BP_GPMI_CTRL0_COMMAND_MODE) & BM_GPMI_CTRL0_COMMAND_MODE)
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#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
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#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
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#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
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#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
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#define BM_GPMI_CTRL0_WORD_LENGTH (1 << 23)
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#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0
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#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1
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/*
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* Difference in LOCK_CS between imx23 and imx28 :
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* This bit may impact the _POWER_ consumption. So some chips
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* do not set it.
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*/
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#define MX23_BP_GPMI_CTRL0_LOCK_CS 22
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#define MX28_BP_GPMI_CTRL0_LOCK_CS 27
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#define LOCK_CS_ENABLE 0x1
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#define BF_GPMI_CTRL0_LOCK_CS(v, x) 0x0
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/* Difference in CS between imx23 and imx28 */
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#define BP_GPMI_CTRL0_CS 20
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#define MX23_BM_GPMI_CTRL0_CS (3 << BP_GPMI_CTRL0_CS)
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#define MX28_BM_GPMI_CTRL0_CS (7 << BP_GPMI_CTRL0_CS)
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#define BF_GPMI_CTRL0_CS(v, x) (((v) << BP_GPMI_CTRL0_CS) & \
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(GPMI_IS_MX23((x)) \
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? MX23_BM_GPMI_CTRL0_CS \
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: MX28_BM_GPMI_CTRL0_CS))
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#define BP_GPMI_CTRL0_ADDRESS 17
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#define BM_GPMI_CTRL0_ADDRESS (3 << BP_GPMI_CTRL0_ADDRESS)
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#define BF_GPMI_CTRL0_ADDRESS(v) \
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(((v) << BP_GPMI_CTRL0_ADDRESS) & BM_GPMI_CTRL0_ADDRESS)
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#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
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#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
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#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
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#define BM_GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16)
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#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0
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#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1
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#define BP_GPMI_CTRL0_XFER_COUNT 0
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#define BM_GPMI_CTRL0_XFER_COUNT (0xffff << BP_GPMI_CTRL0_XFER_COUNT)
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#define BF_GPMI_CTRL0_XFER_COUNT(v) \
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(((v) << BP_GPMI_CTRL0_XFER_COUNT) & BM_GPMI_CTRL0_XFER_COUNT)
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#define HW_GPMI_COMPARE 0x00000010
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#define HW_GPMI_ECCCTRL 0x00000020
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#define HW_GPMI_ECCCTRL_SET 0x00000024
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#define HW_GPMI_ECCCTRL_CLR 0x00000028
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#define HW_GPMI_ECCCTRL_TOG 0x0000002c
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#define BP_GPMI_ECCCTRL_ECC_CMD 13
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#define BM_GPMI_ECCCTRL_ECC_CMD (3 << BP_GPMI_ECCCTRL_ECC_CMD)
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#define BF_GPMI_ECCCTRL_ECC_CMD(v) \
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(((v) << BP_GPMI_ECCCTRL_ECC_CMD) & BM_GPMI_ECCCTRL_ECC_CMD)
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#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE 0x0
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#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE 0x1
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#define BM_GPMI_ECCCTRL_ENABLE_ECC (1 << 12)
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#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1
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#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0
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#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
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#define BM_GPMI_ECCCTRL_BUFFER_MASK (0x1ff << BP_GPMI_ECCCTRL_BUFFER_MASK)
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#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \
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(((v) << BP_GPMI_ECCCTRL_BUFFER_MASK) & BM_GPMI_ECCCTRL_BUFFER_MASK)
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#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100
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#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF
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#define HW_GPMI_ECCCOUNT 0x00000030
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#define HW_GPMI_PAYLOAD 0x00000040
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#define HW_GPMI_AUXILIARY 0x00000050
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#define HW_GPMI_CTRL1 0x00000060
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#define HW_GPMI_CTRL1_SET 0x00000064
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#define HW_GPMI_CTRL1_CLR 0x00000068
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#define HW_GPMI_CTRL1_TOG 0x0000006c
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#define BP_GPMI_CTRL1_DECOUPLE_CS 24
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#define BM_GPMI_CTRL1_DECOUPLE_CS (1 << BP_GPMI_CTRL1_DECOUPLE_CS)
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#define BP_GPMI_CTRL1_WRN_DLY_SEL 22
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#define BM_GPMI_CTRL1_WRN_DLY_SEL (0x3 << BP_GPMI_CTRL1_WRN_DLY_SEL)
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#define BF_GPMI_CTRL1_WRN_DLY_SEL(v) \
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(((v) << BP_GPMI_CTRL1_WRN_DLY_SEL) & BM_GPMI_CTRL1_WRN_DLY_SEL)
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#define BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS 0x0
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#define BV_GPMI_CTRL1_WRN_DLY_SEL_6_TO_10NS 0x1
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#define BV_GPMI_CTRL1_WRN_DLY_SEL_7_TO_12NS 0x2
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#define BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY 0x3
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#define BM_GPMI_CTRL1_BCH_MODE (1 << 18)
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#define BP_GPMI_CTRL1_DLL_ENABLE 17
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#define BM_GPMI_CTRL1_DLL_ENABLE (1 << BP_GPMI_CTRL1_DLL_ENABLE)
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#define BP_GPMI_CTRL1_HALF_PERIOD 16
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#define BM_GPMI_CTRL1_HALF_PERIOD (1 << BP_GPMI_CTRL1_HALF_PERIOD)
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#define BP_GPMI_CTRL1_RDN_DELAY 12
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#define BM_GPMI_CTRL1_RDN_DELAY (0xf << BP_GPMI_CTRL1_RDN_DELAY)
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#define BF_GPMI_CTRL1_RDN_DELAY(v) \
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(((v) << BP_GPMI_CTRL1_RDN_DELAY) & BM_GPMI_CTRL1_RDN_DELAY)
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#define BM_GPMI_CTRL1_DEV_RESET (1 << 3)
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#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0
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#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
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#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2)
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#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0
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#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
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#define BM_GPMI_CTRL1_CAMERA_MODE (1 << 1)
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#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
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#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1
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#define BM_GPMI_CTRL1_GPMI_MODE (1 << 0)
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#define BM_GPMI_CTRL1_CLEAR_MASK (BM_GPMI_CTRL1_WRN_DLY_SEL | \
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BM_GPMI_CTRL1_DLL_ENABLE | \
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BM_GPMI_CTRL1_RDN_DELAY | \
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BM_GPMI_CTRL1_HALF_PERIOD)
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#define HW_GPMI_TIMING0 0x00000070
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#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
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#define BM_GPMI_TIMING0_ADDRESS_SETUP (0xff << BP_GPMI_TIMING0_ADDRESS_SETUP)
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#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \
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(((v) << BP_GPMI_TIMING0_ADDRESS_SETUP) & BM_GPMI_TIMING0_ADDRESS_SETUP)
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#define BP_GPMI_TIMING0_DATA_HOLD 8
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#define BM_GPMI_TIMING0_DATA_HOLD (0xff << BP_GPMI_TIMING0_DATA_HOLD)
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#define BF_GPMI_TIMING0_DATA_HOLD(v) \
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(((v) << BP_GPMI_TIMING0_DATA_HOLD) & BM_GPMI_TIMING0_DATA_HOLD)
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#define BP_GPMI_TIMING0_DATA_SETUP 0
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#define BM_GPMI_TIMING0_DATA_SETUP (0xff << BP_GPMI_TIMING0_DATA_SETUP)
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#define BF_GPMI_TIMING0_DATA_SETUP(v) \
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(((v) << BP_GPMI_TIMING0_DATA_SETUP) & BM_GPMI_TIMING0_DATA_SETUP)
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#define HW_GPMI_TIMING1 0x00000080
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#define BP_GPMI_TIMING1_BUSY_TIMEOUT 16
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#define BM_GPMI_TIMING1_BUSY_TIMEOUT (0xffff << BP_GPMI_TIMING1_BUSY_TIMEOUT)
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#define BF_GPMI_TIMING1_BUSY_TIMEOUT(v) \
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(((v) << BP_GPMI_TIMING1_BUSY_TIMEOUT) & BM_GPMI_TIMING1_BUSY_TIMEOUT)
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#define HW_GPMI_TIMING2 0x00000090
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#define HW_GPMI_DATA 0x000000a0
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/* MX28 uses this to detect READY. */
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#define HW_GPMI_STAT 0x000000b0
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#define MX28_BP_GPMI_STAT_READY_BUSY 24
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#define MX28_BM_GPMI_STAT_READY_BUSY (0xff << MX28_BP_GPMI_STAT_READY_BUSY)
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#define MX28_BF_GPMI_STAT_READY_BUSY(v) \
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(((v) << MX28_BP_GPMI_STAT_READY_BUSY) & MX28_BM_GPMI_STAT_READY_BUSY)
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/* MX23 uses this to detect READY. */
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#define HW_GPMI_DEBUG 0x000000c0
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#define MX23_BP_GPMI_DEBUG_READY0 28
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#define MX23_BM_GPMI_DEBUG_READY0 (1 << MX23_BP_GPMI_DEBUG_READY0)
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#endif
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