forked from Minki/linux
9df11828d9
The L2 cache properties were completely off with respect to what the
hardware is configured for. Fix the cache-size, cache-line-size and
cache-sets to reflect the L2 cache controller we have: 512KB, 16 ways
and 32 bytes per cache-line.
Fixes: 46d4bca044 ("ARM: BCM63XX: add BCM63138 minimal Device Tree")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
136 lines
2.7 KiB
Plaintext
136 lines
2.7 KiB
Plaintext
/*
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* Broadcom BCM63138 DSL SoCs Device Tree
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "brcm,bcm63138";
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model = "Broadcom BCM63138 DSL SoC";
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interrupt-parent = <&gic>;
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aliases {
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uart0 = &serial0;
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uart1 = &serial1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <1>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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arm_timer_clk: arm_timer_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <500000000>;
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};
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periph_clk: periph_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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clock-output-names = "periph";
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};
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};
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/* ARM bus */
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axi@80000000 {
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compatible = "simple-bus";
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ranges = <0 0x80000000 0x784000>;
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#address-cells = <1>;
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#size-cells = <1>;
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L2: cache-controller@1d000 {
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compatible = "arm,pl310-cache";
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reg = <0x1d000 0x1000>;
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cache-unified;
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cache-level = <2>;
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cache-size = <524288>;
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cache-sets = <1024>;
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cache-line-size = <32>;
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interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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scu: scu@1e000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x1e000 0x100>;
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};
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gic: interrupt-controller@1e100 {
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compatible = "arm,cortex-a9-gic";
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reg = <0x1f000 0x1000
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0x1e100 0x100>;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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};
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global_timer: timer@1e200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x1e200 0x20>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&arm_timer_clk>;
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};
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local_timer: local-timer@1e600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x1e600 0x20>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&arm_timer_clk>;
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};
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twd_watchdog: watchdog@1e620 {
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compatible = "arm,cortex-a9-twd-wdt";
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reg = <0x1e620 0x20>;
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interrupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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/* Legacy UBUS base */
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ubus@fffe8000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xfffe8000 0x8100>;
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serial0: serial@600 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x600 0x1b>;
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interrupts = <GIC_SPI 32 0>;
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clocks = <&periph_clk>;
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clock-names = "periph";
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status = "disabled";
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};
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serial1: serial@620 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x620 0x1b>;
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interrupts = <GIC_SPI 33 0>;
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clocks = <&periph_clk>;
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clock-names = "periph";
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status = "disabled";
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};
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};
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};
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